L02 Top Down Design and HDL

L02 Top Down Design and HDL - Top-down Design and Hardware...

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L02 – HDLs 1 6.371 – Fall 2002 09/06/02 Top-down Design and Hardware Description Languages Now I understand what this cover means!
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L02 – HDLs 2 6.371 – Fall 2002 09/06/02 The Need for HDLs A specification is an engineering contract that lists all the goals for a project: ± goals include area, power, throughput, latency, functionality, test coverage, costs (NREs and piece costs), Helps you figure out when you’re done and how to make engineering tradeoffs. Later on, goals help remind everyone (especially management) what was agreed to at the outset! ± top-down design: partition the project into modules with well-defined interfaces so that each module can be worked on by a separate team. Gives the SW types a head start too! ( Hardware/software codesign is currently all the rage…)
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L02 – HDLs 3 6.371 – Fall 2002 09/06/02 The Need for HDLs (cont’d.) A behavioral model serves as an executable functional specification that documents the exact behavior of all the individual modules and their interfaces. Since one can run tests, this model can be refined and finally verified through simulation. We need a way to talk about what hardware should do without actually designing the hardware itself, i.e., we need to separate behavior from implementation. We need a H ardware D escription L anguage If we were then able to synthesize an implementation directly from the behavioral model, we’d be in good shape!
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L02 – HDLs 4 6.371 – Fall 2002 09/06/02 A Tale of Two HDLs VHDL Verilog ADA-like verbose syntax, lots of redundancy (which can be good!) C-like concise syntax Extensible types and simulation engine. Logic representations are not built in and have evolved with time (IEEE-1164). Built-in types and logic representations. Oddly, this led to slightly incompatible simulators from different vendors. Design is composed of entities each of which can have multiple architectures . A configuration chooses what architecture is used for a given instance of an entity. Design is composed of modules . Behavioral, dataflow and structural modeling. Synthesizable subset. .. Behavioral, dataflow and structural modeling. Synthesizable subset. .. Harder to learn and use, not technology-specific, DoD mandate Easy to learn and use, fast simulation, good for hardware design
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L02 – HDLs 5 6.371 – Fall 2002 09/06/02 A VHDL Example library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity GCD is port( signal clk: in std_logic; signal xi, yi: in std_logic_vector(15 downto 0); signal reset: in std_logic; signal gcd: out std_logic_vector(15 downto 0); signal done: out std_logic; ); end GCD; architecture BEHAVIORAL of GCD is begin process(clk) variable x,y: std_logic_vector(15 downto 0); begin if (clk’event and clk=‘1’) then if (reset = ‘1’) then x := xi; y := yi; done <= ‘0’; elsif (done = ‘0’) then if (x = y) then gcd <= x;done <= ‘1’; else if (x > y) then x := x - y; else y := y - x; end if; end if; end if; end process;
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L02 Top Down Design and HDL - Top-down Design and Hardware...

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