L03 Betadiagram

L03 Betadiagram - XAdr ILL OP JT PCSEL 4 3 2 1 0 PC 00...

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PC+4+4*SXT(C) ASEL 0 1 Data Memory RD WD Adr R/W W D SE L 0 1 2 Rc: <25:21> 0 1 XP PC JT +4 Instruction Memory A D Rb: <15:11> Ra: <20:16> RA2SEL + Register File RA1 RA2 RD1 RD2 BSEL 0 1 C: SXT(<15:0>) Z ALU A B JT WA WD WE ALUFN Control Logic Z PCSEL WDSEL Wr PC+4 0 1 0 1 2 3 4 XAdr ILL OP WASEL WASEL IRQ W ER F WERF 00 OP OPC LD ST JMP BEQ BNE LDR Illop trap ALUFN F(op) F(op) “+” “+” — “A” — WERF 1 1 1 0 1 BSEL 0 1
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