{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

L03 Betainst

L03 Betainst - Summary of Instruction Formats Operate Class...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Summary of β Instruction Formats Operate Class: 31 26 25 21 20 16 15 11 10 0 10xxxx Rc Ra Rb unused OP(Ra,Ra,Rc): Reg[Rc] Reg[Ra] op Reg[Rb] Opcodes: ADD (plus), SUB (minus), MUL (multiply), DIV (divided by) AND (bitwise and), OR (bitwise or), XOR (bitwise exclusive or) CMPEQ (equal), CMPLT (less than), CMPLE (less than or equal) [result = 1 if true, 0 if false] SHL (left shift), SHR (right shift w/o sign extension), SRA (right shift w/ sign extension) 31 26 25 21 20 16 15 0 11xxxx Rc Ra literal (two&s complement) OPC(Ra,literal,Rc): Reg[Rc] Reg[Ra] op SEXT(literal) Opcodes: ADDC (plus), SUBC (minus), MULC (multiply), DIVC (divided by) ANDC (bitwise and), ORC (bitwise or), XORC (bitwise exclusive or) CMPEQC (equal), CMPLTC (less than), CMPLEC (less than or equal) [result = 1 if true, 0 if false] SHLC (left shift), SHRC (right shift w/o sign extension), SRAC (right shift w/ sign extension) Other: 31 26 25 21 20 16
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Ask a homework question - tutors are online