L03 More Verilog Examples

L03 More Verilog Examples - Architecture Verilog An...

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L03 – More Verilog 1 6.371 – Fall 2002 09/11/02 Architecture Verilog An Extended Example P C + 4 *S X T (C ) A S E L 0 1 D a ta M e m o ry R W Ad r /W DS EL 2 c: < 5 :2 > JT In s tru c tion b : < :1 6 gis te File B : (< :0 Z LU U F N on trol Lo gic 3 d IL O IR Q ERF always @(posedge clk) begin assign pcinc = pc + 4; u l t ( k , i q I n p [ : ] _ ; f do $ ni h for (i=0; i < 31; i = i+1) begin
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L03 – More Verilog 2 6.371 – Fall 2002 09/11/02 Reprise: Why use an HDL? Want an executable functional specification Document exact behavior of all the modules and their interfaces Executable models can be tested & refined until they do what you want Too much detail at the transistor and mask levels Can’t debug 1M transistors as individual analog components Abstract away “unnecessary” details Play by the rules: don’t break abstraction with clever hacks HDL description is first step in a mostly automated process to build an implementation directly from the behavioral model Logic Synthesis Place & route Verilog Gate netlist Mask HDL logic map to target library optimize speed, area create floorplan blocks place cells in block route interconnect optimize (iterate!)
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L03 – More Verilog 3 6.371 – Fall 2002 09/11/02 Beta redux! PC+4+4*SXT(C) ASEL 0 1 Data Memory RD WD Adr R/W WDSEL 012 WA Rc: <25:21> 0 1 XP PC JT +4 Instruction Memory A D Rb: <15:11> Ra: <20:16> RA2SEL Rc: <25:21> + Register File RA1 RA2 RD1 RD2 BSEL 0 1 C: SXT(<15:0>) Z ALU AB JT WD WE ALUFN Control Logic Z ASEL BSEL PCSEL RA2SEL WDSEL ALUFN Wr PC+4 01 0 1 2 3 4 XAdr ILL OP WASEL WASEL IRQ WERF WERF 00 PCSEL I thought I already did 6.004
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L03 – More Verilog 4 6.371 – Fall 2002 09/11/02 Goals for the Verilog description Readable, correct code that clearly captures the architecture diagram – “correct by inspection” Partition the design into regions appropriate for different implementation strategies. Big issue: wires are “bad” since they take up area and have capacitance (impacting speed and power). Memories: very dense layouts, structured wires pretty much route themselves, just a few base cells to design & verify Datapaths: each cell contains necessary wiring, so replicating cells (for N bits of datapath) also replicates wiring. Data flows between columnar functional units on horizontal busses and control flows vertically. Random logic: interconnect is “random” but library of cells can be designed ahead of time and characterized. Think about physical partition: wires that cross boundaries can take lots of area; blocks have to fit into the floorplan without wasteful gaps. Themes: draw as few fets as possible; maximize use of design techniques that offer good wire management strategies; use special tools for each type of layout
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L03 – More Verilog 5 6.371 – Fall 2002 09/11/02 Hey! What happened to abstraction?
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L03 More Verilog Examples - Architecture Verilog An...

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