L04 Synthesis

L04 Synthesis - Synthesis Verilog Gates in beg r exe or b l...

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L04 – Synthesis 1 6.371 – Fall 2002 09/13/02 Synthesis: Verilog Gates / 2 : 1 m u l t i p e x r a w y s @ ( o b ) g n f z < = ; d I c M A D 0 B L br G
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L04 – Synthesis 2 6.371 – Fall 2002 09/13/02 Synthesis Tools Hey! Shouldn’t that be Synthesys ? Idea : once a behavioral model has been finished why not use it to automatically synthesize a logic implementation in much the same was as a compiler generates executable code from a source program? Synthesis programs process the HDL then a.k.a. “silicon compilers” ± infer logic and state elements ± perform technology-independent optimizations (e.g., logic simplification, state assignment) ± map elements to the target technology ± perform technology-dependent optimizations (e.g., multi-level logic optimization, choose gate strengths to achieve speed goals) Synthesis tools have been under development for many years and now are a generally accepted part of the tool chain. For more info see the lectures at http://www-cad.eecs.berkeley.edu/~mihal/ee244/schedule.html
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L04 – Synthesis 3 6.371 – Fall 2002 09/13/02 Logic Synthesis assign z = (a & b) | c; a b c a b c z z 1 0 b a sel z a b sel z // dataflow assign z = sel ? b : a; // behavioral always @(sel or a or b) begin if (sel) z <= b; else z <= a; end
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L04 – Synthesis 4 6.371 – Fall 2002 09/13/02 Logic Synthesis (II) full adder y[0] x[0] sum[0] 0 full adder y[1] x[1] full adder y[2] x[2] full adder y[3] x[3] sum[1] sum[2] sum[3] cout wire [3:0] x,y,sum; wire cout; assign {cout,sum} = x + y; word[1] word[0] word[2] word[3] parity module parity(in,p); parameter WIDTH = 2; // default width is 2 input [WIDTH-1 : 0] in; output p; // simple approach: assign p = ^in; // here's another, more general approach reg p; always @(in) begin : loop integer i; reg parity = 0; for (i = 0; i < WIDTH; i = i + 1) parity = parity ^ in[i]; p <= parity; end endmodule wire [3:0] word; wire parity; parity #(4) ecc(word,parity); // specify WIDTH = 4 XOR with “0” input has been optimized away…
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L04 – Synthesis 5 6.371 – Fall 2002 09/13/02 Synthesis of Sequential Logic reg q ; // D-latch always @( g or d ) begin if (g) q <= d; end DQ d q g reg q ; // this time we mean it! // D-register always @(posedge clk ) begin q <= d; end d q clk G If Q were simply a combinational function of D, the synthesizer could just create the appropriate combinational logic. But since there are times when the always block executes but Q isn’t assigned (e.g., when G = 0), the synthesizer has to arrange to remember the value of “old” value Q even if D is changing it will infer the need for a storage element (latch, register, …). Sometimes this inference happens even when you don’t mean it to – you have to be careful to always ensure an assignment happens each time through the block if you don’t want storage elements to appear in your design.
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L04 – Synthesis 6 6.371 – Fall 2002 09/13/02 Sequential Logic (II) reg q; // register with asynchronous clear always @( posedge clk or negedge reset) begin if (!reset) // reset is active low q <= 0; else // implicit posedge clk q <= d; end // warning! async inputs are dangerous!
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L04 Synthesis - Synthesis Verilog Gates in beg r exe or b l...

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