L05 CMOS Technology

L05 CMOS Technology - CMOS Technology Only 15,432,758 more...

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L05 – CMOS Technology 1 6.371 – Fall 2002 9/18/02 CMOS Technology Only 15,432,758 more mosfets to do. .. metal pdiff ndiff poly
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L05 – CMOS Technology 2 6.371 – Fall 2002 9/18/02 Basic Fabrication Steps Growing silicon dioxide to serve as an insulator between layers deposited on the surface of the silicon wafer. Doping the silicon substrate with acceptor and donor atoms to create p- and n-type diffusions that form isolating PN junctions and one plate of the MOS capacitor. Depositing material on the wafer to create masks, wires and the other plate of the MOS capacitor. Etching deposited materials to create the appropriate geometric patterns. Figures are from W. Maly, Atlas of IC Technologies: An Introduction to VLSI Processes. (ignore dimensions in figures – they are quite out-of-date!) Figures are from W. Maly, Atlas of IC Technologies: An Introduction to VLSI Processes. (ignore dimensions in figures – they are quite out-of-date!)
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L05 – CMOS Technology 3 6.371 – Fall 2002 9/18/02 Growing Silicon Dioxide O 2 or H 2 O + 900 o to 1100 o Oxygen diffuses thru SiO 2 then oxidizes Si surface Selective growth by using Si 3 N 4 to prevent O 2 from reaching Si surface fast Surface is consumed Thermal oxidation creates high quality film used as mask during diffusion, insulator and gate dielectric. Local oxidation is accomplished using a Si 3 N 4 mask. Bird’s beak reduces size of unoxidized area
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L05 – CMOS Technology 4 6.371 – Fall 2002 9/18/02 Doping by Diffusion Constant Source Two-step: predeposition, drive-in Two-step process results in more uniform concentrations
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L05 – CMOS Technology 5 6.371 – Fall 2002 9/18/02 Doping by Implantation Ion implantation involves much lower process temperatures , much decreased lateral spreading and better control over dopant profile . But surface of wafer is damaged and must be repaired by subsequent thermal annealing step which will redistribute the dopants. Redistribution is minimized with special heating techniques that minimizes exposure of implanted regions. Diffusion still used when dopant profile isn’t critical.
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L05 – CMOS Technology 6 6.371 – Fall 2002 9/18/02 Deposition Is there a lawsuit? Physical vapor deposition to deposit metals (Al, Cu). Chemical vapor deposition to deposit SiO 2 , Si 3 N 4 , single-crystal (epitaxial) and polycrystalline (poly) Si. Nonconformal coverage of steps leads to non-uniform thickness. In metals this can lead to higher current densities in thinner spots which causes current-induced metal migration. Modern approach: planarization.
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L05 – CMOS Technology 7 6.371 – Fall 2002 9/18/02 Etching Photoresist is spun onto wafer then exposed with UV light, X- rays or electron beam (no mask). Develop to remove exposed resist. Wet etching Dry etching isotropic anisotropic Remove photoresist mask Performance note: minimum feature size often determined by photoresist and etching process.
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L05 – CMOS Technology 8 6.371 – Fall 2002 9/18/02 Sources of manufacturing problems Other fab difficulties Ö contacts and vias only on “flat” surfaces Ö no devices near boundaries of well Ö no poly contacts over diffusion
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This note was uploaded on 08/23/2009 for the course EECS 6.371 taught by Professor Krsteasanovic during the Fall '02 term at MIT.

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L05 CMOS Technology - CMOS Technology Only 15,432,758 more...

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