L06 Characterizing CMOS Performance

L06 Characterizing CMOS Performance - Characterizing CMOS...

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L06 – CMOS Performance 1 6.371 – Fall 2002 9/20/02 Characterizing CMOS Performance Wow! 0 to 3.3 volts in 10ps! 1 volt noise margins! No static power dissipation! A free set of Ginzu steak knives! Operators are standing by…
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L06 – CMOS Performance 2 6.371 – Fall 2002 9/20/02 “Bipolar” Logic Isn’t this a CMOS course? V DD V IN V OUT pullup : make this connection when V IN near 0 so that V OUT = V DD ± one power supply => low impedance source for 2 levels ± receiving devices have a simple job => only make one decision ± no DC power if connections not “made” at same time ± Boolean logic has been around a long time Inverter recipe: pulldown : make this connection when V IN near V DD so that V OUT = 0 Why choose a binary (e.g., “0” and “1”) logic system:
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L06 – CMOS Performance 3 6.371 – Fall 2002 9/20/02 CMOS Inverter V in V out D S = 0V G I PD I PD V OUT V IN = 5v I PD vs V OUT for PULLDOWN V IN = 4v V IN = 3v V IN = 2v V IN = 1v S = power supply G D I PU I PU V OUT I PU vs V OUT for PULLUP V IN = 0v V IN = 1v V IN = 2v V IN = 3v V IN = 4v
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L06 – CMOS Performance 4 6.371 – Fall 2002 9/20/02 V in V out V out V in = 0.5V I pu I pd V out V in = 1.5V I pu I pd When both fets are saturated, small changes in V in produce large changes in V out V in = 2.5V V out I pu I pd V in = 4.5V V out I pu I pd V in = 3.5V V out I pu I pd I pu I pd Steady state reached when V out reaches value where I pu = I pd . CMOS Inverter VTC
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L06 – CMOS Performance 5 6.371 – Fall 2002 9/20/02 Can we build a CMOS buffer? V IN V OUT Not like this! Here’s why: V OUT I PU I PU vs V OUT for PULLUP V IN = 5v V IN = 4v V IN = 3v V IN = 2v V IN = 1v I PD I PD vs V OUT for PULLUP V IN = 0v V IN = 1v V IN = 2v V IN = 3v V IN = 4v V OUT V OUT V IN One buffer Two buffers I PU I PD V TH,P V TH,N Nfets turn off when V GS falls below the threshold voltage V TH . So, even if the input voltage is, say, 5V, then the pullup will turn off when V OUT reaches 5V – V TH = 4.2V. The pulldown will also turn off before V OUT reaches 0V.
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L06 – CMOS Performance 6 6.371 – Fall 2002 9/20/02 Characterizing Inverters V IH V IL V OL V OH ± Draw voltage-transfer curve (VTC) for inverter. ± Shade-in areas that VTC can’t enter. ± What can we say about gain? ± What is “ideal” inv. VTC? V in V out What goals do we want to achieve with our inverter implementation (and, more generally, other functions)?
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L06 Characterizing CMOS Performance - Characterizing CMOS...

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