L07 Static CMOS Gates

L07 Static CMOS Gates - Static CMOS Gates F = (A+B).(C+D)...

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L07 – Static CMOS Gates 1 6.371 – Fall 2002 9/25/02 Static CMOS Gates F = (A+B).(C+D)
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L07 – Static CMOS Gates 2 6.371 – Fall 2002 9/25/02 Generic Static CMOS Gate ± For every set of input logic values, either pullup or pulldown network makes connection to VDD or GND If both connected, power rails would be shorted together If neither connected, output would float (tristate logic) V DD IN 1 V OUT IN 2 IN n Pullup network, connects output to V DD , contains only PMOS Pulldown network, connects output to GND, contains only NMOS
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L07 – Static CMOS Gates 3 6.371 – Fall 2002 9/25/02 NAND Gate A B (A.B) ± When both A and B are high, output is low ± When either A or B is low, output is high B A (A.B)
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L07 – Static CMOS Gates 4 6.371 – Fall 2002 9/25/02 NOR Gate A B (A+B) ± When both A and B are low, output is high ± When either A or B is high, output is low A B (A+B)
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L07 – Static CMOS Gates 5 6.371 – Fall 2002 9/25/02 NAND Gate Layout A B (A.B) GND V DD AB (A.B) Series NMOS Transistors Parallel PMOS Transistors Metal 1-Diffusion Contact P-Diffusion (in N-well) N-Diffusion Poly wire connects PMOS & NMOS gates Output on Metal-1
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L07 – Static CMOS Gates 6 6.371 – Fall 2002 9/25/02 Methodical Gate Building ± Goal is to create a logic function f(x 1 , x 2 , . ..) must be inverting for single level of CMOS logic ± Pull up network should connect output to V DD when f(x 1 , x 2 , . ..) = 1 ± Pull down network should connect output to GND when f(x 1 , x 2 , . ..) = 1 ± Because PMOS is conducting with low inputs, useful to write pullup as function of inverted inputs p(x1, x2, . ..) = f(x 1 , x 2 , . ..)
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L07 – Static CMOS Gates 7 6.371 – Fall 2002 9/25/02 Pullup is Dual of Pulldown Network For NAND gate, f=(A.B) ± Pulldown f = A.B ± Pullup p = f = A.B = A+B (De Morgan’s Laws) For NOR gate, f=(A+B) ± Pulldown f = A+B ± Pullup p = f = A+B = A.B A B (A.B) A B
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L07 Static CMOS Gates - Static CMOS Gates F = (A+B).(C+D)...

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