L08 Logical Effort and CMOS Design

L08 Logical Effort and CMOS Design - Logical Effort and...

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L08 – Logical Effort and ASIC Design Styles 1 6.371 – Fall 2002 9/27/02 Logical Effort and ASIC Design Styles
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L08 – Logical Effort and ASIC Design Styles 2 6.371 – Fall 2002 9/27/02 ± Nearly all transistors in digital CMOS circuits have minimum L but might use slightly longer L to cut leakage in parts of modern circuits ± Can scale transistor R and C parameters by width W ± Effective R scales linearly with 1/W ~4k Ωµ m NMOS, ~9k Ωµ m PMOS, in 0.25 µ m technology ± Gate capacitance scales linearly with W ~2fF/ µ m ± Diffusion capacitance scales linearly with W sum contributions from perimeter and area, ~2fF/ µ m Transistor R and C W L G S D Simple Equivalent RC Model of Transistor
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L08 – Logical Effort and ASIC Design Styles 3 6.371 – Fall 2002 9/27/02 Technology Speed Parameter: τ ± Characterize process speed with single delay parameter: τ ± τ is delay of inverter driving same-sized inverter, with no parasitics other than gate τ ~16-20ps for 0.25 µ m process
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L08 – Logical Effort and ASIC Design Styles 4 6.371 – Fall 2002 9/27/02 Gate Delay Components ± Logical Effort Complexity of logic function (Invert, NAND, NOR, etc) Define inverter has logical effort = 1 Depends only on topology not transistor sizing ± Electrical Effort Ratio of output capacitance to input capacitance C out /C in ± Total Effort = Logical Effort x Electrical Effort ± Parasitic Delay Intrinsic self-loading of gate Independent of transistor sizes and output load Logic Gate C in C out Delay = Logical Effort x Electrical Effort + Parasitic Delay
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L08 – Logical Effort and ASIC Design Styles 5 6.371 – Fall 2002 9/27/02 Logical Effort for Simple Gates ± Define Logical Effort of Inverter = 1 ± For other gates, Logical Effort is ratio of logic gate’s input cap. to inverter’s input cap., when gate sized to give same current drive as inverter Equivalently, gives output drive reduction when input cap sized same as inverter 2 1 Relative Transistor Widths 2 2 2 2 1 4 4 1 Inverter Input Cap = 3 units L.E.=1 (definition) NAND Input Cap = 4 units L.E.=4/3 NOR Input Cap = 5 units L.E.=5/3
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L08 – Logical Effort and ASIC Design Styles 6 6.371 – Fall 2002 9/27/02 Electrical Effort ± Ratio of output load capacitance over input capacitance: Electrical Effort = C out /C in ± Usually, transistors have minimum length ± Input and output capacitances can be measured in units of transistor gate widths Logic Gate C in C out
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L08 – Logical Effort and ASIC Design Styles 7 6.371 – Fall 2002 9/27/02 Parasitic Delay ± Main cause is drain capacitances ± These scale with transistor width so P.D. independent of transistor sizes ± Useful approximation: C gate ~= C drain ± For inverter: Parasitic Delay ~= 1.0 τ ± For n-input NAND/NOR Parasitic Delay ~= n τ (only include drains on output node) C drainN R onN C gateN C drainP R onP C gateP
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L08 – Logical Effort and ASIC Design Styles 8 6.371 – Fall 2002 9/27/02 Optimizing Circuit Paths ± Path logical effort, G = Π g i (g i = L.E. stage i) ± Path electrical effort, H = C out /C in (h i = E.E. stage i) ± Parasitic delay, P = Σ p i (p i = P.D. stage i)
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L08 Logical Effort and CMOS Design - Logical Effort and...

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