L10 Clocks

L10 Clocks - Clocking and Storage Elements 6.371 Fall 2002...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
L10 – Clocks 1 6.371 – Fall 2002 10/4/02 Clocking and Storage Elements
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
L10 – Clocks 2 6.371 – Fall 2002 10/4/02 Why Clocks and Storage Elements? Inputs Outputs Combinational Logic Want to reuse combinational logic from cycle to cycle
Background image of page 2
L10 – Clocks 3 6.371 – Fall 2002 10/4/02 Digital Systems Timing Conventions ± All digital systems need a convention about when a receiver can sample an incoming data value synchronous systems use a common clock asynchronous systems encode “data ready” signals alongside, or encoded within, data signals ± Also need convention for when it’s safe to send another value synchronous systems, on next clock edge (after hold time) asynchronous systems, acknowledge signal from receiver Data Clock Data Ready Acknowledge Synchronous Asynchronous
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
L10 – Clocks 4 6.371 – Fall 2002 10/4/02 Large Systems ± Most large scale ASICs, and systems built with these ASICs, have several synchronous clock domains connected by asynchronous communication channels Chip A Chip B Chip C Clock domain 1 Clock domain 4 Clock domain 2 Clock domain 3 Clock domain 5 Clock domain 6 Asynch. channel ± We’ll focus on a single synchronous clock domain for this lecture
Background image of page 4
L10 – Clocks 5 6.371 – Fall 2002 10/4/02 Clocked Storage Elements Transparent Latch, Level Sensitive data passes through when clock high, latched when clock low Clock DQ Clock D Q Transparent Latched Clock Clock D Q D-Type Register or Flip-Flop, Edge-Triggered data captured on rising edge of clock, held for rest of cycle (Can also have latch transparent on clock low, or negative-edge triggered flip-flop)
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
L10 – Clocks 6 6.371 – Fall 2002 10/4/02 Building a Latch 1 0 CLK D Q Latches are a mux, clock selects either data or output value D’ Q Optional output buffer Optional input buffer CMOS Transmission Gate Latch Parallel N and P transistors act as switch, called a “transmission gate” CLK CLK CLK D Q Usually have local inverter to generate CLK
Background image of page 6
L10 – Clocks 7 6.371 – Fall 2002 10/4/02 Static CMOS Latch Variants D CLK CLK CLK CLK Q Clocked CMOS (C 2 MOS) feedback inverter
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 24

L10 Clocks - Clocking and Storage Elements 6.371 Fall 2002...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online