L11 Domino Logic

L11 Domino Logic - Domino Logic 6.371 Fall 2002 10/9/02 L11...

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L11 – Domino Logic 1 6.371 – Fall 2002 10/9/02 Domino Logic
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L11 – Domino Logic 2 6.371 – Fall 2002 10/9/02 Tinkering with Logic Gates Things to like about CMOS gates: ± easy to translate logic to fets ± rail-to-rail switching ± good noise margins, no static power since fets are in cutoff ± sizing not critical to correct operation Things not to like about CMOS gates: ± N inputs Ö 2N fets (i.e., one nfet and one pfet) ± large circuit area, especially for pfets, “heavy” loading of inputs ± pfets are either large or slow relative to nfets ± series connections can get very slow We can replace pfet pullup network with pseudo-NMOS load (pfet with grounded gate) but ± dissipate static power when output is low ± have to make load fet small to ensure that V OL is low enough to cut off nfets in next stage ± reduces static power consumption (good!) ± increases output rise time (bad!) One alternative: dynamic CMOS gates A B
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L11 – Domino Logic 3 6.371 – Fall 2002 10/9/02 Dynamic CMOS Gates A B A B CLK “precharge” switch “evaluate” switch When CLK is low ± evaluate nfet is off and precharge pfet is on ± output node is precharged to V DD , other nodes may precharge to V DD -V th,n depending on values of inputs When CLK goes high ± evaluate nfet is on and precharge pfet is off ± output node may be discharged if inputs have configured a conducting path to GND, otherwise output node stays charged high. ± inputs must be stable before CLK goes high because once output has been discharged it won’t go high again until next cycle ± for same reason, noise/glitches on inputs cannot exceed nfet threshold, a much more stringent requirement than for static CMOS gates.
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L11 – Domino Logic 4 6.371 – Fall 2002 10/9/02 There’s good news and bad news The good news: Dynamic gates are faster than static gates despite the extra “evaluate” fet in the pulldown path because of the reduction in self-loading and the elimination of the pullup short-circuit current during the first part of the output transition. The bad news: Dynamic gates cannot be cascaded. CLK nfets nfets CLK Because of finite pulldown time for node , node starts to discharge! Solution – develop techniques that avoid races: CMOS Domino logic, CMOS NORA (no race) logic
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L11 – Domino Logic 5 6.371 – Fall 2002 10/9/02 CMOS Domino Logic CLK nfets nfets precharge:low evaluate: rises (maybe) buffer might be needed in any case for high fan-out circuits. When CLK is low, dynamic node is precharged high and buffer inverter output is low. Nfets in the next logic block will be off. When CLK goes high, dynamic node is conditionally discharged and the buffer output will conditionally go high. Since discharge can only happen once, buffer output can only make one low-to-high transition.
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L11 Domino Logic - Domino Logic 6.371 Fall 2002 10/9/02 L11...

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