L12 CMOS Layout

L12 CMOS Layout - CMOS Layout Measure twice, fab once 6.371...

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L12 – CMOS Layout 1 6.371 – Fall 2002 10/16/02 CMOS Layout Measure twice, fab once
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L12 – CMOS Layout 2 6.371 – Fall 2002 10/16/02 Lambda-based design rules One lambda = one half of the “minimum” mask dimension, typically the length of a transistor channel. Usually all edges must be “on grid”, e.g., in the MOSIS scalable rules, all edges must be on a lambda grid. 1 2 3 2 1 2 2 3 2x2 3 3 2 1 2x2 3 poly metal1 diffusion (active) contact More info at: http://www.mosis.org/Technical/Designrules/scmos/scmos-main.html
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L12 – CMOS Layout 3 6.371 – Fall 2002 10/16/02 Sample “Lambda” Layout λ AY vss vdd
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L12 – CMOS Layout 4 6.371 – Fall 2002 10/16/02 Sample Sea-of-Gates Layout vss nfets pfets vdd pfets nfets vss Column showing all possible contact locations
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L12 – CMOS Layout 5 6.371 – Fall 2002 10/16/02 Lamba vs. Micron rules Lambda-based design rules are based on the assumption that one can scale a design to the appropriate size before manufacture. The assumuption is that all manufacturing dimensions scale equally , an assumption that “works” only over some modest span of time. For example: if a design is completed with a poly width of 2 λ and a metal width of 3 λ then minimum width metal wires will always be 50% wider than minimum width poly wires. Consider the following data from Weste , Table 3.2: contacted metal pitch 1/2 * contact size contact surround metal-to-metal spacing contact surround 1/2 * contact size lambda rule 1 λ 1 λ 3 λ 1 λ 1 λ 8 λ lambda = 0.5u 0.5 µ 0.5 µ 1.5 µ 0.5 µ 0.5 µ 4 µ micron rule 0.375 µ 0.5 µ 1.0 µ 0.5 µ 0.375 µ 2.75 µ Scaled design is legal but much larger than it needs to be!
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L12 – CMOS Layout 6 6.371 – Fall 2002 10/16/02 Retargetable Layouts So, should one use lambda rules, or not? ± probably okay for retargeting between “similar” processes, e.g., when later process is a simple “shrink” of the earlier process. This often happens between generations as a mid-life kicker for a process. Some 0.35u processes are shrinks of an earlier 0.5u process. Can be useful for “fabless” semiconductor companies. ± most industrial designs use micron rules to get the extra space efficiency. Cost of retargeting by hand is acceptable for a successful product, but usually it’s time for a redesign anyway. ± invent some way of entering a design symbolically but use a more sophisticated technique for producing the masks for a particular process. Insight: relative sizes may change but topological relationship between components does not . So, instead of shrinking a design, compact it! LED offers compaction for leaf cells. ..
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L12 – CMOS Layout 7 6.371 – Fall 2002 10/16/02 Sticks and Compaction Stick diagram Horizontal constraints for compaction in X Compact X then Y Compact Y then X Compact X with jog insertion, then Y
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L12 – CMOS Layout 8 6.371 – Fall 2002 10/16/02 Choosing a “style” Vertical Gates Good for circuits where fets sizes are similar and each gate has limited fanout.
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L12 CMOS Layout - CMOS Layout Measure twice, fab once 6.371...

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