L13 CMOS Memories

L13 CMOS Memories - CMOS Memories I wonder which part does...

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L13 – CMOS Memories 1 6.371 – Fall 2002 10/18/02 CMOS Memories I wonder which part does the remembering?
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L13 – CMOS Memories 2 6.371 – Fall 2002 10/18/02 Semiconductor Memories Read-only memories: ROM (non-volatile!) Mask programmed, Programmable ROM (PROM), Erasable PROM (EPROM), Electrically Erasable PROM (EEPROM) Read/Write or Random Access memories: RAM Static RAM (SRAM) Multiport SRAM (Register Files), Content-Addressable Memories (CAM) Non-volatile SRAM (NVRAM) Dynamic RAM (DRAM) Serial-access video memories (VRAM), Synchronous DRAM (SDRAM), Double-data rate DRAM (DDRAM) RAMBUS (RDRAM) ... Usually the majority of transistors found in a modern system are devoted to data storage in the form of random-access memories. The need for increased densities and lower prices has driven the development of improved VLSI technology. Uses: “main” memory high capacity, low cost cache memories, TLB’s fast access programming info (eg, FPGA) non-volatile
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L13 – CMOS Memories 3 6.371 – Fall 2002 10/18/02 Design Tradeoffs density: bits/unit area. Usually higher density also means lower cost per bit. Improvements due to finer lithography, better capacitor structures, new materials with higher dielectric constants. Speed: access time (latency) and bandwidth. Improvements due to better sensing (smaller voltage swing), increased parallelism (overlapped accesses), faster I/O. Power consumption: want power to depend on access pattern not quantity of bits stored. Improvements due to lower supply voltage. Improvements in one dimension come at an increased cost in the other dimensions. Improvements in one dimension come at an increased cost in the other dimensions.
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L13 – CMOS Memories 4 6.371 – Fall 2002 10/18/02 Memory Architecture Row Address Decoder Col. 1 Col. 2 Col. 3 Col. 2 M Row 1 Row 2 Row 2 N Column Decoder M N N+M bit lines word lines memory cell (one bit) D DATA ± Most memory layouts are “folded”, i.e., D < 2 M . Why? ± What are there practical upper bounds on M and N? ± What if you want even more memory? ± Why only one bit per cell? (Not a silly question!) ± Why are “page-mode” accesses a good idea?
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L13 – CMOS Memories 5 6.371 – Fall 2002 10/18/02 ROM Circuits R1 R2 R3 R4 C1 C2 C3 C4 NOR-based ROM array shared ground shared bit line contact R1 1 0 0 0 R2 0 1 0 0 R3 0 0 1 0 R4 0 0 0 1 C1 0 0 1 0 C2 1 0 0 1 C3 0 1 0 1 C4 1 1 1 0
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L13 – CMOS Memories 6 6.371 – Fall 2002 10/18/02
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This note was uploaded on 08/23/2009 for the course EECS 6.371 taught by Professor Krsteasanovic during the Fall '02 term at MIT.

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L13 CMOS Memories - CMOS Memories I wonder which part does...

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