L18 Clocking

L18 Clocking - Clocking Part 2 6.371 Fall 2002 11/6/02 L18...

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L18 – Clocks Part 2 1 6.371 – Fall 2002 11/6/02 Clocking Part 2
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L18 – Clocks Part 2 2 6.371 – Fall 2002 11/6/02 Clocking ± For modern processors, cycle time is around 16- 20 FO4 delays, of which registers take 2-4 FO4 delays ± Power consumption dominated by clock load, both distribution network and end loads (latches, prechargers) 70% of total power in IBM POWER4 design ± Simple single-edge triggered registers are fine for most ASIC designs. This lecture we’ll examine what is happening in high performance designs.
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L18 – Clocks Part 2 3 6.371 – Fall 2002 11/6/02 Edge Triggered Timing Constraints ± Slow path timing constraint T cyc T CQmax + T Pmax + T setup + T skew worst case is when CLK2 is earlier/later than CLK1 ± Fast path timing constraint T CQmin + T Pmin T hold + T skew worst case is when CLK2 is earlier/later than CLK1 ± Fast path constraint cannot be fixed by slowing clock – fatal to chip design ± Skew reduces cycle time Combinational Logic T Pmin /T Pmax CLK1 CLK2
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L18 – Clocks Part 2 4 6.371 – Fall 2002 11/6/02 Two Phase Latch Based Design ± Divide cycle into two phases phase 2 latches can only sample values generated from phase 1 latch outputs, and vice versa. ± Latches driven by two non-overlapping clocks ± Can guarantee no fast path problems with larger non-overlap Combinational Logic 1 CLK1 Combinational Logic 2 CLK1 CLK2 CLK2 CLK1 Non-overlap times
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L18 – Clocks Part 2 5 6.371 – Fall 2002 11/6/02 Two Phase Timing ± In steady state, T z T x , therefore minimum cycle time T cyc T P1max + T P2max + 2 × T DQmax ± Non-overlap time, T NO
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This note was uploaded on 08/23/2009 for the course EECS 6.371 taught by Professor Krsteasanovic during the Fall '02 term at MIT.

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L18 Clocking - Clocking Part 2 6.371 Fall 2002 11/6/02 L18...

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