L19 Case Study part1

L19 Case Study part1 - L19 Case Study T0 1 6.371 Fall 2002...

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Unformatted text preview: L19 Case Study T0 1 6.371 Fall 2002 11/8/02 Case Study: T0 Vector Microprocessor L19 Case Study T0 2 6.371 Fall 2002 11/8/02 Background and Motivation Speech researchers at the International Computer Science Institute in Berkeley, CA, were training large neural networks to estimate phoneme probabilities. Each run required massive computation (workstation-years). In 1989, a Sparcstation-1 could perform around 1 MCUPS (million connection updates per second). First ICSI system RAP, (Ring Array Processor) used up to 40 commercial DSPs connected with Xilinx parts to get higher performance, 100 MCUPS, but cost $100,000 each. Neural net algorithms could be run in fixed-point arithmetic (8-bit and 16-bit) and are highly data parallel. Goal was to build a high performance single chip processor that could run neural net algorithms as fast as RAP, but was small enough and cheap enough to fit inside each speech researchers workstation. L19 Case Study T0 3 6.371 Fall 2002 11/8/02 Earlier Group Projects 1990 HiPNeT-1 (Highly Pipelined Neural Trainer) Full-custom application-specific circuit for binary neural network training in 2.0 m CMOS. Test chips fully functional at 25MHz. Speech algorithms changing too fast cant design new chip for each research algorithm. 1991 Fast Datapath (Group class project, turned into Bertrand Irissous Masters thesis) 64-bit integer RISC datapath in 1.2 m CMOS Goal was highest speed possible, using extensive dynamic logic and aggressive latch design (very similar design philosophy to Alpha which was under design at same time) Chips worked at 180-220MHz (around 10 FO4 cycle time)...
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This note was uploaded on 08/23/2009 for the course EECS 6.371 taught by Professor Krsteasanovic during the Fall '02 term at MIT.

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L19 Case Study part1 - L19 Case Study T0 1 6.371 Fall 2002...

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