L19 Case Study part2

L19 Case Study part2 - Day 2 VLSI Microprocessor Design...

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Day 2 VLSI Microprocessor Design Flow Session A: Circuit design styles Break Session B: Design paths Lunch Session C: Verification Break Session D: Manufacture, fabrication testing, packaging
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Today Organized Bottom-Up Circuit design style Full-custom design path Standard cell design path RTL design Verification strategy Packaging Manufacture & testing Important: real designs proceed at all levels simultaneously
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T0 Circuit Design Style Typical design style for modern microprocessor Datapaths and memories Control logic Full-custom layout Standard cells Regular structures Irregular structures Most of the die area Most of the complexity Few design bugs Most of the design bugs Mostly hand-specified procedural layout and routing (some hand layout and routing) Placed and routed automatically Sometimes exotic circuit designs (dynamic, self-timed) Conservative static CMOS circuits
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T0 Die Breakdown Std. Cell Full-Custom
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Global Design Style Decisions Extremely important: Clock methodology and latch design Power, ground, and clock distribution Must be settled early since these affect every circuit on the chip.
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T0 Clock and Latch Style Input clock signal at 2x on-chip frequency (e.g., 80MHz crystal for 40MHz Spert-II board) divided by 2 on-chip to guarantee 50% duty cycle. Clock buffered up, last stage drives single clock grid across entire chip, <1ns skew across chip, <500ps rise/fall time. Clock output pad to phase lock external circuitry to T0 clock. TSPC dynamic latches (T0 has minimum operating frequency). Also, some special pseudo-static load-enabled latches. Very similar to Alpha 21064 clocking strategy.
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T0 Clock Distribution 2x Clock Input Clock Buffer Clock Grid (In reality hundreds of wires) Clock Output
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T0 Latch Style Standard-cell controller designed with edge-triggered flip-flops • Only negative edge-triggered flip-flops • Simpler for state machines • Simplifies synthesis timing specification • State stall handled with mux around flip-flop - no clock gating Full-custom datapaths and memories used transparent latches • p- and n- type latches transparent on clock low or high respectively • Can steal time across clock cycle boundaries • Can place latches in convenient place in signal flow to save area • Simplifies double-cycling (used in vector register file, some buses) • Special stallable n-latch (small area without clock gating) Designed library of latches verified to operate across all process corners with clock skew/rise/fall spec, and when placed in series with other latches.
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T0 Power/Ground Distribution Half of all pins were power and ground (204/408) Chip-on-board packaging gave low-inductance path to board (~1nH per wire) Grid across whole chip in wide M1 and M2 strapped whereever possible.
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L19 Case Study part2 - Day 2 VLSI Microprocessor Design...

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