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lecture26 - Lecture#26 ANNOUNCEMENTS Extra Office Hours...

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Lecture 26, Slide 1 EECS40, Fall 2003 Prof. King Lecture #26 ANNOUNCEMENTS Extra Office Hours this week : Prof. King: Thursday 10/30 12-2 PM Steve: Friday 10/31 12-2 PM – Farhana: Review session : Friday 10/31 2-4 PM, 120 Latimer OUTLINE Logic functions NMOS logic gates The CMOS inverter Reading Schwarz & Oldham: Chapters 11.2, 15.3 • Rabaey et al .: Chapter 5.2 Lecture 26, Slide 2 EECS40, Fall 2003 Prof. King Digital Signals For a digital signal, the voltage must be within one of two ranges in order to be defined: Positive Logic: – “ low” voltage logic state 0 – “high” voltage logic state 1 “1” “0” V OH V IH V IL V OL undefined region increasing voltage V DD 0 Volts
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Lecture 26, Slide 3 EECS40, Fall 2003 Prof. King Logic Functions, Symbols, & Notation “NOT” F = A TRUTH NAME SYMBOL NOTATION TABLE F A 1 1 1 0 0 1 0 1 0 0 0 0 F B A “OR” F = A+B F A B 0 1 1 0 F A 1 1 1 1 0 1 1 1 0 0 0 0 F B A “AND” F = A•B F A B Lecture 26, Slide 4 EECS40, Fall 2003 Prof. King “NOR” F = A+B 0 1 1 1 0 1 1 1 0 0 0 0 F B A “NAND” F = A
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