lecture27 - Lecture#27 ANNOUNCEMENTS Extra Office Hours...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Lecture 27, Slide 1 EECS40, Fall 2003 Prof. King Lecture #27 ANNOUNCEMENTS • Extra Office Hours this week: – Prof. King: Thu. 10/30 1:15-2 PM – Steve: Fri. 10/31 12-2 PM – Farhana: Sat. 11/1 4-5 PM; Sun. 11/2 3-5 PM (regular office hours cancelled next week) OUTLINE – The CMOS inverter (cont’d) – CMOS logic gates – The body effect Reading (Rabaey et al. ) Chapter 5.5.1 (p.174); 6.2.1 (pp.199-202); Chapter 3.3.2 (pp.58-60) Lecture 27, Slide 2 EECS40, Fall 2003 Prof. King Features of CMOS Circuits • The output is always connected to V DD or GND in steady state Full logic swing; large noise margins Logic levels are not dependent upon the relative sizes of the devices (“ ratioless ”) • There is no direct path between V DD and GND in steady state no static power dissipation
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Lecture 27, Slide 3 EECS40, Fall 2003 Prof. King The CMOS Inverter: Current Flow during Switching V IN V OUT V DD V DD 0 0 N: off P: lin N: lin P: off N: lin P: sat N: sat P: lin N: sat P: sat A BD E C i i S D G G S D V DD V OUT V IN Lecture 27, Slide 4 EECS40, Fall 2003 Prof. King
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 6

lecture27 - Lecture#27 ANNOUNCEMENTS Extra Office Hours...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online