lecture29 - Lecture #29 ANNOUNCEMENTS Lab project: Bring a...

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Lecture 29, Slide 1 EECS40, Fall 2003 Prof. King Lecture #29 ANNOUNCEMENTS • Lab project : – Bring a check ($50, payable to “UC Regents”) to lab this week in order to receive your Tutebot kit. (You will receive this back, when you return the kit.) – Extra credit will be awarded if you endow your Tutebot with additional “intelligence”! • Prof. King’s office hour tomorrow (11/6) is cancelled OUTLINE – Synthesis of logic circuits – Minimization of logic circuits Reading Lecture 29, Slide 2 EECS40, Fall 2003 Prof. King Combinational Logic Circuits • Logic gates combine several logic-variable inputs to produce a logic-variable output. Combinational logic circuits are “memoryless” because their output value at a given instant depends only on the input values at that instant. • Next time, we will study sequential logic circuits that possess memory because their present output value depends on previous as well as present input values.
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Lecture 29, Slide 3 EECS40, Fall 2003 Prof. King Boolean Algebra Relations A•A = A A•A = 0 A•1 = A
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lecture29 - Lecture #29 ANNOUNCEMENTS Lab project: Bring a...

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