lecture32

# lecture32 - Lecture #32 ANNOUNCEMENTS Midterm #2: x = 35.8...

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Lecture 32, Slide 1 EECS40, Fall 2003 Prof. King Lecture #32 ANNOUNCEMENTS • Midterm #2 : x = 35.8 (71.6%); σ =6.9; hi=47.5; lo=13 • (Midterm#1: x = 44.4 (88.8%); σ =7.2; hi=50; lo=10) • HW#9, Problem 3b : Assume t p << 1 (negligible on timing diagram) OUTLINE • Computing the output capacitance – Propagation delay examples • History of IC devices and technology Reading (Rabaey et al .) : Chapter 5.4, pp. 158-163 Lecture 32, Slide 2 EECS40, Fall 2003 Prof. King MOSFET Layout and Cross-Section Top View : Cross Section :

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Lecture 32, Slide 3 EECS40, Fall 2003 Prof. King Source and Drain Junction Capacitance C source = C j × (AREA) + C jsw × ( PERIMETER) = C j L S W + C JSW (2 L S + W ) Lecture 32, Slide 4 EECS40, Fall 2003 Prof. King Computing the Output Capacitance In Out Metal1 V DD GND Poly-Si PMOS W / L =9 λ /2 λ In Out Example 5.4 (pp. 161-163) NMOS W / L =3 λ /2 λ 2 λ =0.25 µ m
Lecture 32, Slide 5 EECS40, Fall 2003 Prof. King In Out V DD GND PMOS W / L =9 λ /2 λ NMOS W / L =3 λ /2 λ 2 λ =0.25 µ m Capacitances for 0.25 µ m technology: Gate capacitances : •C ox (NMOS) = C ox (PMOS) = 6 fF/ µ m 2 Overlap capacitances : • CGDO(NMOS) = C on = 0.31fF/ µ m • CGDO(PMOS)= C op = 0.27fF/ µ m Bottom junction capacitances : •CJ(NMOS)±=±K eqbpn C j = 2 fF/ µ m 2 •CJ(PMOS)±=±K eqbpp C j = 1.9 fF/ µ m 2 Sidewall junction capacitances : •CJSW(NMOS)±=±K eqswn C j = 0.28fF/ µ m •CJSW(PMOS)±=±K eqbpp C j = 0.22fF/ µ m Lecture 32, Slide 6 EECS40, Fall 2003 Prof. King

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Lecture 32, Slide 7 EECS40, Fall 2003 Prof. King Examples of Propagation Delay ~20 ps 3.2 GHz 0.13 µ m Pentium IV ~40 ps 1.8 GHz 0.18 µ m Pentium III ~100 ps 600 MHz 0.25 µ m Pentium II Fan-out=4 inverter delay Clock frequency, f CMOS technology generation Product
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## This note was uploaded on 08/23/2009 for the course EECS 40 taught by Professor Chang-hasnain during the Fall '08 term at Berkeley.

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lecture32 - Lecture #32 ANNOUNCEMENTS Midterm #2: x = 35.8...

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