Lecture35 - Lecture#35 OUTLINE Device isolation methods Electrical contacts to Si Mask layout conventions Process flow examples Resistor N-channel

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Lecture 35, Slide 1 EECS40, Fall 2003 Prof. King Lecture #35 OUTLINE Device isolation methods Electrical contacts to Si Mask layout conventions Process flow examples –Res is to r – N-channel MOSFET Lecture 35, Slide 2 EECS40, Fall 2003 Prof. King Device Isolation Methods The substrate is biased to ensure that the pn junctions are never forward biased p n Top View : p p p (1) pn-junction isolation: Cross-Sectional View : n device area 1 device area 2 pp depletion region
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Lecture 35, Slide 3 EECS40, Fall 2003 Prof. King SiO 2 n device area 1 device area 2 SiO 2 (2) Oxide isolation: p p SiO 2 dielectric substrate ( e.g. SiO 2 , Al 2 O 3 ) (3) Silicon-on-Insulator substrate: Si Si device area 1 device area 2 Lecture 35, Slide 4 EECS40, Fall 2003 Prof. King Electrical Contacts to Si • In order to achieve a low-resistance (“ohmic”) contact between metal and silicon, the silicon must be heavily doped: SiO 2 Al n-type Si SiO 2 n+ N D 10 20 cm -3 Metal contact to n-type Si SiO 2 Al p-type Si SiO 2 p+ N A 10 19 cm -3 Metal contact to p-type Si Æ To contact the body of a MOSFET, locally heavy doping is used.
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Lecture 35, Slide 5 EECS40, Fall 2003 Prof. King Mask Layout • Typically, multiple lithography steps are needed in order to fabricate an integrated circuit. – Each lithography step utilizes a mask with the desired pattern for a specific layer.
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This note was uploaded on 08/23/2009 for the course EECS 40 taught by Professor Chang-hasnain during the Fall '08 term at University of California, Berkeley.

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Lecture35 - Lecture#35 OUTLINE Device isolation methods Electrical contacts to Si Mask layout conventions Process flow examples Resistor N-channel

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