l3_verilog_comb

l3_verilog_comb - L3: Introduction to Verilog...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
L3: 6.111 Spring 2007 1 Introductory Digital Systems Laboratory L3: Introduction to L3: Introduction to Verilog Verilog (Combinational Logic) (Combinational Logic) Acknowledgements : Rex Min Verilog References: Samir Palnitkar, Verilog HDL , Pearson Education (2nd edition). Donald Thomas, Philip Moorby, The Verilog Hardware Description Language , Fifth Edition, Kluwer Academic Publishers. J. Bhasker, Verilog HDL Synthesis (A Practical Primer) , Star Galaxy Publishing
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
L3: 6.111 Spring 2007 2 Introductory Digital Systems Laboratory Verilog Synthesis and Synthesis and HDLs HDLs input a,b; output sum; assign sum = {1b’0, a} + {1b’0, b}; FPGA PAL ASIC (Custom ICs) ± Hardware description language (HDL) is a convenient, device- independent representation of digital logic Netlist g1 "and" n1 n2 n5 g2 "and" n3 n4 n6 g3 "or" n5 n6 n7 ± HDL description is compiled into a netlist ± Synthesis optimizes the logic ± Mapping targets a specific hardware platform Compilation and Synthesis Mapping
Background image of page 2
L3: 6.111 Spring 2007 3 Introductory Digital Systems Laboratory Verilog Verilog : The Module : The Module ± Verilog designs consist of interconnected modules . ± A module can be an element or collection of lower level design blocks. ± A simple module with combinational logic might look like this: Declare and name a module; list its ports. Don’t forget that semicolon. Specify each port as input, output, or inout Express the module’s behavior. Each statement executes in parallel; order does not matter. module mux_2_to_1(a, b, out, outbar, sel); // This is 2:1 multiplexor input a, b, sel; output out, outbar; assign out = sel ? a : b; assign outbar = ~out; endmodule Conclude the module code. 2-to-1 multiplexer with inverted output 1 0 sel out outbar a b Comment starts with // Verilog skips from // to end of the line Out = sel a + sel b
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
L3: 6.111 Spring 2007 4 Introductory Digital Systems Laboratory Continuous (Dataflow) Assignment Continuous (Dataflow) Assignment ± Continuous assignments use the assign keyword ± A simple and natural way to represent combinational logic ± Conceptually, the right-hand expression is continuously evaluated as a function of arbitrarily-changing inputs…just like dataflow ± The target of a continuous assignment is a net driven by combinational logic ± Left side of the assignment must be a scalar or vector net or a concatenation of scalar and vector nets. It can’t be a scalar or vector register ( discussed later ). Right side can be register or nets ± Dataflow operators are fairly low-level: ² Conditional assignment: (conditional_expression) ? (value-if-true) : (value-if-false); ² Boolean logic: ~, &, | ² Arithmetic: +, -, * ± Nested conditional operator (4:1 mux) ² assign out = s1 ? (s0 ? i3 : i2) : (s0? i1 : i0); module mux_2_to_1(a, b, out, outbar, sel); input a, b, sel; output out, outbar; assign out = sel ? a : b; assign outbar = ~out; endmodule 1 0 sel out outbar a b
Background image of page 4
L3: 6.111 Spring 2007 5 Introductory Digital Systems Laboratory Gate Level Description Gate Level Description module muxgate (a, b, out, outbar, sel); input a, b, sel; output out, outbar; wire out1, out2, selb; and a1 (out1, a, sel); not i1 (selb, sel); and a2 (out2, b , selb);
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 26

l3_verilog_comb - L3: Introduction to Verilog...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online