l5_simple_seq_verilog

# l5_simple_seq_verilog - L5 Simple Sequential Circuits and...

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L5: 6.111 Spring 2007 1 Introductory Digital Systems Laboratory L5: Simple Sequential Circuits and L5: Simple Sequential Circuits and Verilog Verilog Acknowledgements: Nathan Ickes and Rex Min

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L5: 6.111 Spring 2007 2 Introductory Digital Systems Laboratory Key Points from L4 (Sequential Blocks) Key Points from L4 (Sequential Blocks) Classification: ± Latch: level sensitive (positive latch passes input to output on high phase, hold value on low phase) ± Register: edge-triggered (positive register samples input on rising edge) ± Flip-Flop: any element that has two stable states. Quite often Flip-flop also used denote an (edge-triggered) register D Clk Q Q D D Clk Q Q D Positive Register Positive Latch ± Latches are used to build Registers (using the Master-Slave Configuration), but are almost NEVER used by itself in a standard digital design flow. ± Quite often, latches are inserted in the design by mistake (e.g., an error in your Verilog code). Make sure you understand the difference between the two. ± Several types of memory elements (SR, JK, T, D). We will most commonly use the D-Register, though you should understand how the different types are built and their functionality.
L5: 6.111 Spring 2007 3 Introductory Digital Systems Laboratory System Timing Parameters System Timing Parameters D Clk Q In Combinational Logic D Clk Q Logic Timing Parameters Register Timing Parameters T logic : worst case delay through the combinational logic network T logic,cd : contamination or minimum delay through logic network T cq : worst case rising edge clock to q delay T cq, cd : contamination or minimum delay from clock to q T su : setup time T h : hold time

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L5: 6.111 Spring 2007 4 Introductory Digital Systems Laboratory System Timing (I): Minimum Period System Timing (I): Minimum Period D Clk Q In Combinational Logic D Clk Q CLK T su T h T su T h T cq T cq,cd T cq T cq,cd FF1 IN CLout CLout T l,cd T su2 T logic T > T cq + T logic + T su
L5: 6.111 Spring 2007 5 Introductory Digital Systems Laboratory System Timing (II): Minimum Delay System Timing (II): Minimum Delay D Clk Q In Combinational Logic D Clk Q CLK T su T h T h T cq,cd FF1 IN CLout T l,cd T cq,cd + T logic,cd > T hold CLout

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L5: 6.111 Spring 2007 6 Introductory Digital Systems Laboratory The Sequential The Sequential always always Block Block ± Edge-triggered circuits are described using a sequential always block Combinational Sequential module combinational(a, b, sel, out); input a, b; input sel; output out; reg out; always @ (a or b or sel) begin if (sel) out = a; else out = b; end endmodule module sequential(a, b, sel, clk, out); input a, b; input sel, clk; output out; reg out; always @ (posedge clk) begin if (sel) out <= a; else out <= b; end endmodule 1 0 sel 1 0 sel out a DQ a out b b clk
L5: 6.111 Spring 2007 7 Introductory Digital Systems Laboratory Importance of the Sensitivity List Importance of the Sensitivity List ± The use of posedge and negedge makes an always block sequential (edge-triggered) ± Unlike a combinational always block, the sensitivity list does determine behavior for synthesis!

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## This note was uploaded on 08/23/2009 for the course EECS 6.111 taught by Professor Prof.ananthachandrakasan during the Spring '04 term at MIT.

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l5_simple_seq_verilog - L5 Simple Sequential Circuits and...

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