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l11_system_integration

l11_system_integration - L11 Major/Minor FSMs...

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L11: 6.111 Spring 2007 1 Introductory Digital Systems Laboratory L11: Major/Minor L11: Major/Minor FSMs FSMs Acknowledgements: Rex Min
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L11: 6.111 Spring 2007 2 Introductory Digital Systems Laboratory Quiz Quiz Quiz will be Closed Book Tuesday, March 20, 2007 , 7:30pm-9:30pm in 32-155 Covers Problem Sets 1-3, Lectures 1-9 (through Arithmetic), Labs 1-3 Some of the topics to be covered include Combinational Logic: Boolean Algebra, Karnaugh Maps, MSP, MPS, dealing with don’t cares Latches and Edge Triggered Registers/Flip-flops z Understand the difference between latches, registers and unclocked memory elements (e.g., SR-Flip Flop) z Different memory types: SR, D, JK, T z Understand setup/hold/propagation delay and how they are computed System Timing (minimum clock period and hold time constraint) z Impact of Clock skew on timing Counters and simple FSMs (understand how the ‘163 and ‘393 work) FSM design (Mealy/Moore, dealing with glitches) Combinational and sequential Verilog coding z Continuous assignments, blocking vs. non-blocking, etc.
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L11: 6.111 Spring 2007 3 Introductory Digital Systems Laboratory Quiz (cont.) Quiz (cont.) Tri-states basics Dealing with glitches z When are glitches OK?
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  • Spring '04
  • Prof.AnanthaChandrakasan
  • Key signature, Relative key, Digital Systems Laboratory, Introductory Digital Systems, Introductory Digital Systems Laboratory, minor fsm

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