L15_digital_logic

# L15_digital_logic - 6.02 Spring 2008 Digital Logic Slide 1...

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Unformatted text preview: 6.02 Spring 2008 Digital Logic, Slide 1 Digital Logic • Combinational circuits • Digital Signaling • Truth tables, sum of products • INV-AND-OR circuits • NAND/NOR circuits • MUXes • Propagation delay 6.02 Spring 2008 Digital Logic, Slide 2 A Digital Processing Element Static discipline Output a “1” if at least 2 out of 3 of my inputs are a “1”. Otherwise, output “0”. I will generate a valid output in no more than 2 minutes after seeing valid inputs input A input B input C output Y • A combinational device is a circuit element that has – one or more digital inputs – one or more digital outputs – a functional specification that details the value of each output for every possible combination of valid input values – a timing specification consisting (at minimum) of an upper bound t pd on the required time for the device to compute the specified output values from an arbitrary set of stable, valid input values 6.02 Spring 2008 Digital Logic, Slide 3 A Combinational Digital System • A set of interconnected elements is a combinational device if – each circuit element is a combinational device – every input is connected to exactly one output or a constant (eg, some vast supply of 0’s and 1’s) – the circuit contains no directed cycles • Why is this true? Given an acyclic circuit meeting the above constraints, we can derive functional and timing specs for the input/output behavior from the specs of its components! 6.02 Spring 2008 Digital Logic, Slide 4 Digital Signaling We can encode information using voltages, currents, frequency, phase, etc. A common choice is to use a voltage encoding and a binary (0/1) signaling scheme. Recalling our strategy when discussing the digital abstraction: • encode 0/1 as two voltages (aka valid logic levels) • allow room for noise to happen: noise margins • use forbidden zone to separate valid logic levels DEVICE #2 DEVICE #1 How should we encode information on this wire? 6.02 Spring 2008 Digital Logic, Slide 5 Digital Signaling II OUTPUTS: INPUTS: Forbidden Zone volts 0 V DD V OL OUT 1 OUT V OH volts 0 V DD V IL IN 1 IN V IH V OL V OH Noise Margins Let’s leave room for bad things to happen! So we’ll design devices restore marginally valid input signals. They must accept marginal inputs and provide unquestionable outputs (i.e., to leave room for noise)....
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## This note was uploaded on 08/23/2009 for the course EECS 6.02 taught by Professor Terman during the Spring '08 term at MIT.

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L15_digital_logic - 6.02 Spring 2008 Digital Logic Slide 1...

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