L17_reg_pipelining

L17_reg_pipelining - Registers & Pipelining ! Intro to...

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6.02 Spring 2008 Registers & Pipelining, Slide 1 Registers & Pipelining Intro to registers Register+logic example: FIR filter Cut-set retiming: transposed filters Pipelining, throughput, latency 6.02 Spring 2008 Registers & Pipelining, Slide 2 Our last component: the D register D Q D CLK Q D CLK Q The edge-triggered D register: on the rising edge of CLK , the value of D is saved in the register and then shortly afterwards appears on Q.
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6.02 Spring 2008 Registers & Pipelining, Slide 3 D-Register Timing - I CLK D Q D Q D CLK Q <t PD t PD : maximum propagation delay, CLK ! Q >t SETUP t SETUP : setup time How long D must be stable before the rising edge of CLK >t HOLD t HOLD : hold time How long D must be stable after the rising edge of CLK 6.02 Spring 2008 Registers & Pipelining, Slide 4 D-Register Timing - II CLK t PD,reg1 logic D Q D Q CLK reg1 reg2 t PD,logic t PD,reg1 + t PD,logic + t SETUP,reg2 ! t CLK t CLK " t SETUP,reg2
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6.02 Spring 2008 Registers & Pipelining, Slide 5 Multi-bit & Load-enabled Registers N N 0 1 N-2 N-1 0 1 N-2 N-1 CLK D Q CLK D Q CLK D LE N N Q N N D Q 0 1 LE CLK N LE = Load Enable This register only loads a new value when LE = 1. 6.02 Spring 2008 Registers & Pipelining, Slide 6 Single-clock Synchronous Circuits Single-clock Synchronous Discipline No combinational cycles Only care about value of combinational circuits just before rising edge of clock Period greater than every combinational delay Change saved state after noise-inducing logic transitions have stopped! We’ll use Registers in a highly constrained way to build
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This note was uploaded on 08/23/2009 for the course EECS 6.02 taught by Professor Terman during the Spring '08 term at MIT.

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L17_reg_pipelining - Registers & Pipelining ! Intro to...

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