This preview shows pages 1–2. Sign up to view the full content.
6.02 Spring 2008
1 of 3
Homework #8
M
ASSACHUSETTS
I
NSTITUTE OF
T
ECHNOLOGY
D
EPARTMENT OF
E
LECTRICAL
E
NGINEERING AND
C
OMPUTER
S
CIENCE
6.02 Introduction to EECS II
Spring 2008
Homework #8: Arithmetic Circuits & Registers
Issued: April 4, 2008
Due: April 11, 2008
Problem 1
.
Calculate the following using 6bit 2's complement arithmetic (which is just
a fancy way of saying to do ordinary addition in base 2 keeping only 6 bits of your
answer). Show your work using binary (base 2) notation. Remember that subtraction can
be performed by negating the second operand and then adding it to the first operand.
13 + 10
15  18
27  6
6  15
21 + (21)
31 + 12
Explain what happened in the last addition and in what sense your answer is "right".
Problem 2
.
Suppose we have two 2’s complement numbers, one of N bits and one of M
bits (without loss of generality let N
≥
M).
What is the minimum number of bits needed
to represent the sum of the two numbers without any loss of information?
What about the
product of the two numbers?
Problem 3
.
Consider the following diagram of a simple sequential circuit:
The components labeled CL1 and CL2 are combinational; R1 and R2 are edgetriggered
D registers.
Timing parameters for component are as noted (we’re ignoring the registers’
This preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
This is the end of the preview. Sign up
to
access the rest of the document.
This note was uploaded on 08/23/2009 for the course EECS 6.02 taught by Professor Terman during the Spring '08 term at MIT.
 Spring '08
 Terman
 Computer Science, Electrical Engineering

Click to edit the document details