Class02_Signal_Parameters_I

# Class02_Signal_Parameters_I - S ignal and Tim Param te I...

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Signal and Timing Parameters I Common Clock – Class 2 Prerequisite Reading assignment: CH8 to 9.3 Acknowledgements: Intel Bus Boot Camp:  Howard Heck

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Signal Parameters & Timing Class 2 2 Agenda Voltage and Time Budgets Computer Signaling Elements and Circuits Flight time Synchronous Bus Operation Clock Skew and Jitter Setup and Hold Manufacturing Considerations Advanced Topics
Signal Parameters & Timing Class 2 3 Voltage and time SI boils down to meeting voltage and time specifications True for most I/O computer interfaces Violating a time or voltage specification i.e. exceeding a limit, may cause a circuit to fail Notice the use of the word “may” rather than “will” Most limits are at least 3 sigma limits. The actual sigma limits are usually a company secret. Margin is the difference between a specification and the respective measured signal parameter. Margin is considered a quality factor for a design.

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Signal Parameters & Timing Class 2 4 SI Budgets An SI budget is a technique used to report timing and voltage margin in terms of voltage and timing components (“buckets”) for all configurations and conditions of a particular bus design. The budget is often represented in a spread sheet. Margin Voltage Spec Noise Bucket Measured Voltage Measurement Error 14 100 10 56 20 (mv) =B2-(C2+D2+E2) … Cell formula
Signal Parameters & Timing Class 2 5 What Failing SI Means: Negative margin - limit + limit Mean Probability that a parameter is a certain value Measured parameter The integral of the probability function outside these limits is the  failing population Pf X volume X cost/unit = variable cost of failure Not the whole story – A bad name can cost billions in fixed costs  (good will)

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Signal Parameters & Timing Class 2 6 Simple I/O Architecture Pre- ’00 the most common computer I/O interface was synchronous memory transfer Intel Xeon 100 MHz bus was just about the last in this class Clock distribution is a challenge – more on this later CPUs RAM Memory  & I/O control clock
Signal Parameters & Timing Class 2 7 Synchronous Memory Elements - Operation Operation A data signal ( in ) that is present at the input to the flip-flop is “latched” into the flip-flop by the rising edge of the input clock signal ( clk ). On the next rising edge of clk , the data signal is released to the output of the flip-flop ( out ). This means data is clocked out of device a on one clock edge and received at device b on the next clock edge. This is also called common clocking. Memory Memory Inter- connect Device a Device b out in clk Edge Triggered Flip Flop input data output data clock

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Signal Parameters & Timing Class 2 8 Synchronous Memory Elements - Timing Timing Valid data must be present for a minimum amount of time prior to the input clock edge to guarantee successful capture of the data. This is T setup T hold clk in
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## Class02_Signal_Parameters_I - S ignal and Tim Param te I...

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