class11 - 1 CMOS Inverters Lecture 2 Dr. Jerry L. Hudgins...

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8/12/03 Transistor Review 1 CMOS –Inverters Lecture 2 Dr. Jerry L. Hudgins Department of Electrical Engineering University of South Carolina
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8/12/03 Transistor Review 2 Supply Voltage Effects
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8/12/03 Transistor Review 3 Gain as a Function of V DD 0 0.05 0.1 0.15 0.2 0 0.1 0.15 0.2 V in (V) V ou t (V ) 0 0.5 1 1.5 2 2.5 0 1 2 V out Gain = -1 The gain can be improved by lowering the supply voltage, however, below a few tenths of a volt, the gain deteriorates.
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8/12/03 Transistor Review 4 Effects of Reducing the Supply Voltage ± Gain improves ± Energy dissipation is lowered ± Reduces internal noise (crosstalk) ± dc characteristics become sensitive to variations in device parameters ± Increases sensitivity to external noise ± Increases the propagation delay times!
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8/12/03 Transistor Review 5 Supply Voltage Effect on Propagation Delay Average equivalent resistance during the load capacitance discharge. + = DD DD V V DD Dsat DD Dsat DD eq V I V dV V I V V R 2 / 9 7 1 4 3 ) 1 ( 2 / 1 λ = 2 ) ( 2 ' DSsat DSsat t DD Dsat V V V V L W k I Ignoring channel-length modulation factor: ) 2 / ( ) / ( 52 . 0 4 3 69 . 0 69 . 0 ' Dsatn Tn DD Dsatn n n n DD L Dsatn DD L HL L eqn pHL V V V V k L W V C I V C C R t = = = 2 / Dsatn Tn DD DD po pHL V V V V t t × =
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8/12/03 Transistor Review 6 Supply Voltage Effect on Propagation Delay 733 . 0 2 / × = × = DD DD po Dsatn Tn DD DD po pHL V V t V V V V t t Note that supply voltages below 1.1 V cause an enormous increase in the propagation delay.
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8/12/03 Transistor Review 7 Propagation Delay Effects from Sizing
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8/12/03 Transistor Review 8 Transient Response Ti me 0s 100ps 200ps 300ps 400ps 500ps V( 2 ) V( 3 ) 0V 2. 0V -1.0V 3. 0V t pHL t pLH
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8/12/03 Transistor Review 9 A CMOS Inverter * .MODEL nch NMOS + LEVEL=3 PHI=0.70 TOX=1.0E-08 XJ=0.20U TPG=1 + VTO=0.8 DELTA=2.5E-01 LD=4.0E-08 KP=1.88E-04 + UO=545 THETA=2.5E-01 RSH=2.1E+01 GAMMA=0.62 + NSUB=1.4E+17 NFS=7.1E+11 VMAX=1.9E+05 ETA=2.2E-02 + KAPPA=9.7E-02 CGDO=3.7E-10 CGSO=3.7E-10 CGBO=4.0E-10 + CJ=5.4E-04 MJ=0.6 CJSW=1.5E-10 MJSW=0.3 PB=0.99 * .MODEL pch PMOS + LEVEL=3 PHI=0.70 TOX=1.0E-08 XJ=0.20U TPG=-1 + VTO=-0.9 DELTA=2.5E-01 LD=6.7E-08 KP=4.45E-05 + UO=130 THETA=1.8E-01 RSH=3.4E+00 GAMMA=0.52 + NSUB=9.8E+16 NFS=6.5E+11 VMAX=3.1E+05 ETA=1.8E-02 + KAPPA=6.3E+00 CGDO=3.7E-10 CGSO=3.7E-10 CGBO=4.3E-10 + CJ=9.3E-04 MJ=0.5 CJSW=1.5E-10 MJSW=0.3 PB=0.95 * M1 3 2 0 0 nch W=4u L=0.6u AS=7.2p PS=7.6u AD=7.2p PD=7.6u M2 3 2 1 1 pch W=5.5u L=0.6u AS=9.9p PS=9.1u AD=9.9p PD=9.1u CL 3 0 0.006pF * VDD 1 0 2.5V VIN 2 0 PULSE(0 2.5 0 10p 10p 150p 1n) * .TRAN 0.005n 1n * .DC VIN 0V 2.5V 0.01V * .PROBE * .END
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This note was uploaded on 08/23/2009 for the course ECLT 762 taught by Professor Yinchaochen during the Spring '03 term at South Carolina.

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class11 - 1 CMOS Inverters Lecture 2 Dr. Jerry L. Hudgins...

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