Class23-24_Vias_Connectors_and_Packages

Class23-24_Vias_Connectors_and_Packages - Vias, C ctors,...

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  Vias, Connectors, and Packages Prerequisite Reading Assignment Chapter 5
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2 Introduction 2 How are signal getting from one chip to another? Pentium 4 goes here (socket) Memory Connector Bridge chip Vias, connectors, and packages are all important and necessary parts of the path. The PWB traces connect between these. Bridge chip package
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3 Introduction 3 Agenda Vias Definition: what are they and why do we need them? Electrical models of via parastics Connectors Definition: what are they and why do we need them? Electrical effects Inductance SLEM-style approximation Power and ground pins Design considerations (tradeoffs, rules of thumb)
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4 Introduction 4 Agenda, continued Packages Definition: what they are and why we need them Common types (e.g. flip-chip, bondwire) and history Creating package models Effect of a package on signal integrity Design considerations
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5 Introduction 5 capacitor chip chip Printed Circuit Board Vertical connections between layers made by drilling a small hole and filling it with conductive material. These exist connecting metal layers on Silicon chips, within packages, and on printed circuit boards. Vias Vias
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6 Introduction 6 Via : vertical connection between layers Barrel: conductive cylinder filling the drilled hole Pad: connects the barrel to the component/plane/trace Antipad: clearance hole between via and no-connect metal layer Barrel Pad Via pad does not contact plane; void is the anti-pad Trace connected to pad on layer 1.
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7 Introduction 7 A Via might: Connect metal planes of the same potential (e.g., all ground planes conductively attached) Carry a signal from a trace on one layer to another (e.g., every data signal must get from the silicon bump down to the motherboard…and possibly through the motherboard!) Connect components (such as a capacitor) to a signal trace or a voltage plane.
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8 Introduction 8 PCB via types Buried Via Buried Via Through Hole Via Through Hole Via Blind Via Blind Via Stacked Via Stacked Via Step Via Step Via
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9 Introduction 9 SEM cross-sections Laser generated via Photo-defined via Plasma generated via Cond. ink filled via
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10 Introduction 10 SEM Cross-sections microvia Plated-through hole
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11 Introduction 11 L_barrel C_pad C_pad Model of a Via Vias are tiny structures, and unless T_ via delay > 1/10 [signal edge] the via can be modeled as a lumped pi-model. To dark pink t-line To pink t-line
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12 Introduction 12 Cascading elements L_barrel C_pad C_pad L_barrel C_pad Trace connection Trace connection
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13 Introduction 13 Via Capacitance Effect is to slow the edge Empirical formula for pad capacitance: Via Inductance Series L degrades signal integrity Empirical formula for barrel inductance: 1 2 1 41 . 1 D D T D C r via - = ε ] 1 4 [ln 08 . 5 + = d h h L via D 1 Via pad diameter D 2 Via anti-pad diameter T PCB thickness h via length d barrel diameter Via induced delay: capacitive loading + added distance
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Class23-24_Vias_Connectors_and_Packages - Vias, C ctors,...

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