Class2_3_4_Clocking

Class2_3_4_Clocking - Clocking Lecture 2 and 3 Purpose...

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12/4/2002   Clocking – Lecture 2 and 3  Purpose – Clocking Design Topics Read Chapter 12
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12/4/2002 Introduction 2 Optional Additional Reading http://www.uoguelph.ca/~antoon/gadgets/pll/pll.ht   © by Tony van Roon http://www.cwc.nus.edu.sg/news/semin
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12/4/2002 Introduction 3 Agenda Clock Signal Requirements Intro to Phase Lock Loop – Baby Steps Clock Circuit Examples
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12/4/2002 Introduction 4 In a system design, clocks may be generated by  external chips The idea assumption is that the clock edge are synchronized at each  device A digital clock signal is ideally a 50% duty cycle square wave A “ clock domain”   is comprised of the a set of signals that are  referenced to the same idea clock signal. CPUs RAM Memory  & I/O control clock
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12/4/2002 Introduction 5 Clock Signal Requirements Monotonic edges Avoid double clocking and meta-stable behavior.  Controlled with distribution topology Fast edges   Reduce uncertainty from slew rate  Controlled by length Low Skew Controlled by topology, loading, and receiver sensitivity. Low Jitter Mostly a clock generation issue. High fan-out - Topology Includes cpu’s, i/o chips, expansion connectors, memory chips,  control chips
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12/4/2002 Introduction 6 Non-monotonic series terminated effects Threshold limits Wave is reflected at  the load and turns  around here Wave is re-reflected at  the source due to  imperfect termination  and transmitted back  to load. This “bump” move up and down depending  on relation to Zl, Zs, rterm, and Zo. So we can see how more than just time delay  effects the clock skew
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12/4/2002 Introduction 7 Fast Edge Reduce Skew – but… Fast edges can reduce the time uncertainty through  the thresholds However stub and packages can make fast edges more  susceptible to ringing which can cause double clocking  of the data
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12/4/2002 Introduction 8 Issues with single ended threshold sensitivity The wave is referenced to either Vcc or Vss. Consequently the effective  DC value of the wave will be tied to one of these rails. The wave is attenuated around the effective DC component of the  waveform, but the reference does not change accordingly. Hence the  clock trigger point between various clock load points is very sensitive to  distortion and attenuation. Vss Vss Vss Rx1 Rx2 Tx Vref Vref Vref
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12/4/2002 Introduction 9 Differential Clocking vs Single Ended Clocking Greater detail will be covered in in the next course.
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This note was uploaded on 08/23/2009 for the course ECLT 865 taught by Professor Yinchaochen during the Spring '03 term at South Carolina.

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Class2_3_4_Clocking - Clocking Lecture 2 and 3 Purpose...

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