Class2_1_2_behavioral_CMOS_Modeling

Class2_1_2_behavioral_CMOS_Modeling - Be havioral Buffe...

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12/4/2002   Behavioral Buffer Modeling with HSPICE – Intel Buffer 10-08-03
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12/4/2002 Introduction 2 Objective Demonstrate alternative HSPICE behavioral simulation methods. Can be used when the present features of IBIS models are insufficient. Can be used for pre-silicon feature design characterization in a system environment.
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12/4/2002 Introduction 3 Topics Behavioral Driver models Close gap between technology and IBIS Convergence Advisory Circuits with that use switches and G elements tend to be more susceptive to convergence problems. High speed differential behavioral buffer and input characterization is an extension of these methods
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12/4/2002 Introduction 4 Simple CMOS Model Rn Rp Cn Components: Complementary Pulse source Switch Resistor Capacitor DC source Ground
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12/4/2002 Introduction 5 Assignment - 1 Create simple CMOS model Use Pspice Rp=10 ohm, Rn=10 ohms Adjust Cn to get a 1 ns risetime (20% to 80%) with a 50 ohm load and 1pf tied to ground Hint: Use a 100MHz, 50% duty cycle for the pulse source.
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12/4/2002 Introduction 6 Behavioral Model Test Program Start with “testckt” file from pervious class MYBUFF will be our new generator DATAS will modified for different rise and fall times. Printed Wiring Board Buffers package Receiver Data generator “MYBUF” “DATAS”
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12/4/2002 Introduction 7 Level 1 Behavioral Model Control PWL VCCS Vss Control PWL VCCS Vdd 0V 0 Buffer Pad Buffer Pad 1.0 V 1.0 V Profile conditioner Profile conditioner 01001100  PWL source Math Process to  create edges in in balancen out V V R R - = 1 * ) ( in in balancep out V V R R - = 1 * ) ( “MYBUF” “DATAS”
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12/4/2002 Introduction 8 Data pattern generator Syntax: changed to yield different bit waveforms with different rise and fall times.
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12/4/2002 Introduction 9 Bit data waveform
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12/4/2002 Introduction 10 Creating a simple equation based V-T wave The bit pattern is used to create a representative PWL data wave . A proportional unity driving waveform (v-t wave) is created out of the PWL pulse. The edge of the ramp of the PWL pulse is proportional to the time for the bit transition. The entire transition of the pulse is related to the rise/fall time of the wave. 1.0 V 01001100  pulse(t) wave t ( ) 1 e pulse t ( ) ( ) wf - 2.4 - 1.1 = bits
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12/4/2002 Introduction 11 Syntax HSPICE for driver The circuit is completed with the voltage profile derived from  the  unity driving waveform  which controls a dependant  resistor tied to the n and p loads. In this case the loads are 50  ohms. We need to insure we don’t divide by zero and also do  not result in an exact 0 ohm resistance.
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Class2_1_2_behavioral_CMOS_Modeling - Be havioral Buffe...

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