Class2_5_6_IO_Power_delivery2

Class2_5_6_IO_Power_delivery2 - I/O Power Delivery...

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Unformatted text preview: 12/4/2002 I/O Power Delivery Background Reading Chap 12.12, 13.7 Hall, Hall & McCall Chap. 6.2 12/4/2002 I/O Power Delivery 2 Power Delivery Introduction In general power delivery analysis at the board level is very difficult. Determining the voltage at any point in time on an entire board is akin to predicting the weather. There are fairly good estimation methods for determining the effects of chip load, power planes, and capacitors. Determining effects of signaling on the board power becomes very complex. Chip manufacturers have reasonably good methods for determining the power delivery to the silicon from the board. This is only for a single chip. We will call this the traditional analysis The second and more interesting topic is the effect of I/O switching on chip power and vice versa. 12/4/2002 I/O Power Delivery 3 Topics We will introduce the traditional methods first, then spend most of the time on I/O power delivery. The method we will talk about in the I/O power delivery section will be simple but illustrates some profound effects. Power delivery “noise” can create EMI which we will not cover. Robust treatment of power delivery is a great topic for research. One point to consider is that ideal power delivery is an impedance of 0 ohms between generation and utilization. Now consider that measuring impedances near 0 ohms has a number of challenges. Again another good topic for research. 12/4/2002 I/O Power Delivery 4 Traditional Power Delivery Analysis The traditional method is basically evaluating the step response of the PDN (power delivery network) A simple outline of the simulation steps is as follows. Create system model May be reduced to simple RLC ladder. More complete analysis may use bed-spring models or S parameters. The die is divided into di/dt regions. In simulation place di/dt loads at the die regions with voltage controlled resistors driven by scaled current steps. Then evaluate waveform regions of the largest specified step response This analysis is usually focused on the charge cycle. The high di/dt creates a demand. We need to measure how well the rest of the PDN works to stabilize the voltage. This is done by evaluating each droop and then trying to associate it with each PDN design domain. 12/4/2002 I/O Power Delivery 5 Example of Simple Traditional Method Regulator Board High current di/dt ~ amps/microsecond We just look for droops and spike on the delivered power rail 12/4/2002 I/O Power Delivery 6 Resonance Traditional analysis does not comprehend feedback and interaction between data switching and PDN resonance. The di/dt are aggregate responses from silicon blocks of relatively uncorrelated switching of millions very small transistors....
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This note was uploaded on 08/23/2009 for the course ECLT 865 taught by Professor Yinchaochen during the Spring '03 term at South Carolina.

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Class2_5_6_IO_Power_delivery2 - I/O Power Delivery...

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