project_part3 - SoC Design Laboratory Term Project Part III...

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IEE 5637 SoC Design Lab., 2004 1 SoC Design Laboratory Term Project Part III Rapid Prototyping for Baseline H.264 decoder Instructor: Tian-Sheuan Chang Announcement: 2005.05.31 Due date: 2004.06.28 In the final part of the term project, you will prototype the baseline H.264 decoder using ARM integrator. You will need to implement your deblocking filter IP on the Logic Module, and then integrate it with the software. As a result, your H.264 decoder should include both hardware and software. Make sure that your decoder uses the AMBA-compliant hardware IP you designed in part II. Note: The required HDL files for programming the FPGA on the Logic Module are provided for your reference. Examples for AHB bus interface and structure in Logic Module can be found in Install\Logic Modules\LM-XCV600E\ (e.g., C:\Program Files\ARM\Logic Modules\LM-XCV600E\) of PC. The following documents can be helpful for your project. LM-XCV600E User Guide,
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project_part3 - SoC Design Laboratory Term Project Part III...

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