05_IP_SOC_Verification_new

05_IP_SOC_Verification_new - T ia n-S h e u a n C h a n g...

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Unformatted text preview: T ia n-S h e u a n C h a n g IP V e r i f ic a t io n IP/SOC Verification T ia n-S h e u a n C h a n g Copyright ©2003 All rights reserved 1 IP V e r i f ic a t io n Outline • Verification challenges • Verification process • Verification tools • RTL logic simulation • RTL formal verification • Verifiable RTL – good stuff • Verifiable RTL – bad stuff • Testbench design • SOC verification T ia n-S h e u a n C h a n g Copyright ©2003 All rights reserved 2 IP V e r i f ic a t io n Verification Challenges (1) • Verification goals is 100% correct – Mission impossible • Macro-level testbenches and test suite must be reusable – For next redesigned macro – For integration team • Verified in standalone as well as in final applications • Testbench must be compatible with the system level verification tools T ia n-S h e u a n C h a n g Copyright ©2003 All rights reserved 3 IP V e r i f ic a t io n Verification Challenge (2) Hardware Design Productivity 20 40 60 80 100 120 140 160 1 9 8 1 9 8 2 1 9 8 4 1 9 8 6 1 9 8 8 1 9 9 1 9 9 2 1 9 9 4 1 9 9 6 1 9 9 8 Year Gates Per Day • Design Productivity has risen tenfold since 1990 – Gain by synthesis tools contributed to this challenge • Only able to verify approximately 100 gates/day T ia n-S h e u a n C h a n g Copyright ©2003 All rights reserved 4 IP V e r i f ic a t io n Verification Challenge (3) IC/ASIC Designs Having One or More Re-spins by Type of Flaw 4% 13% 17% 17% 20% 21% 23% 25% 28% 29% 67% 35% 0% 10% 20% 30% 40% 50% 60% 70% Other Firmware Power Race Condition IR Drops Mixed-Signal Interface Yield Clocking Slow Path Noise Analog Circuit Logic or Functional Source: Collett International Research (Apr02) T ia n-S h e u a n C h a n g Copyright ©2003 All rights reserved 5 IP V e r i f ic a t io n Re-spins are EXPENSIVE 2,000 4,000 6,000 8,000 10,000 Costs ($K) Proto & Validation Support SW Physical Design Verification Design Planning IP Dev and Qual Spec Plus a) lost revenue, b) opportunity costs Plus a) lost revenue, b) opportunity costs Source: International Business Strategies, 2002 $10.7M $10.7M $4.7M $4.7M Original Re-spin T ia n-S h e u a n C h a n g Copyright ©2003 All rights reserved 6 IP V e r i f ic a t io n Verification and Design Reuse • Reuse is about trust • The key to design reuse is gaining that trust • Verification for Reuse – Complete functional verification – All possible configurations – All possible uses T ia n-S h e u a n C h a n g Copyright ©2003 All rights reserved 7 IP V e r i f ic a t io n Outline • Verification challenges • Verification process • Verification tools • RTL logic simulation • RTL formal verification • Verifiable RTL – good stuff • Verifiable RTL – bad stuff • Testbench design • SOC verification T ia n-S h e u a n C h a n g Copyright ©2003 All rights reserved 8 IP V e r i f ic a t io n Boosting Productivity throughout the Verification Flow Lint Checking Test Bench Simulation with Assertion...
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This note was uploaded on 08/23/2009 for the course IEE 5016 taught by Professor Tian-sheuanchang during the Spring '05 term at National Chiao Tung University.

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05_IP_SOC_Verification_new - T ia n-S h e u a n C h a n g...

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