c1_basics

c1_basics - Principles of VLSI Design Basics CMPE 413 1...

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Unformatted text preview: Principles of VLSI Design Basics CMPE 413 1 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 MOS: Metal-Oxide-Silicon Metal gate has been replaced by polysilicon or poly in today’s processes. Can be used as a further mask to allow precise dfinition of the source and drain regions. Minimizes gate-to-source/drain overlap which is good for performance. MOS structure created by superimposing several layers of conducting, insu- lating and transistor-forming materials. Construction process is carried out on a SINGLE crystal of silicon. Wafers are 15-20 cm in diameter (6-8 inches). CMOS: Two types of transistors are used, pMOS and nMOS. nMOS: negatively doped silicon, rich in electrons. pMOS: positively doped silicon, rich in holes (the DUAL of electrons). Principles of VLSI Design Basics CMPE 413 2 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 An nMOS transistor Source Drain Gate R s R d W L V GS V DS Thin Oxide n+ n+ p-substrate n-channel GND Drain Source I DS I DS GND diffusion Principles of VLSI Design Basics CMPE 413 3 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Inverter Cross-section n+ n+ p+ glass p substrate m2 m1 m1-m2 contact p-substrate contact V DD n-diffusion contact polysilicon gate n-transistor p-transistor GND n-substrate contact p-diffusion contact (source) (source) (Out) (In) layer #1 layer #2 layer #3 n+ p+ p+ n-well (drains) Principles of VLSI Design Basics CMPE 413 4 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 MOS Transistor Switches: WecantreatMOStransistorsassimpleon-offswitcheswithasource(S),gate (G) (controls the state of the switch) and drain (D). Let ‘1’ represent high voltage, 1.5V to 15V (<= 3.3V today) (V DD ). Let ‘0’ represent low voltage - GND or V SS . Signals such as ‘1’ and ‘0’ have strength , measures their ability to: • Sink (to lower voltage, e.g. GND) or • Source (from higher voltage, e.g. V DD ) current. nMOS and pMOS signal transmission strength: 1 1 1 *** Strong *** Weak Weak *** Strong *** 1 nMOS pMOS S D S D G G Principles of VLSI Design Basics CMPE 413 5 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 MOS Transistor Switches: Thereasonp-transistorsarepoortransmittersoflogic0andn-transistorsare poor transmitters of logic 1 is related to threshold voltage (V t ~= 700mV). Threshold voltage is defined and discussed in detail in Chapter 2. Under the “switch” abstraction, G has complete control and S and D have no effect. Inreality,thegatecanturntheswitchononlyifapotentialdifference of at least V t exists between the G and S. This is clearly not the case for the “weak” bias configurations and “weak” 0s (~700mV) and “weak” 1s (~4.3V) result. The following (buffer) implementation is a BAD IDEA. Why? Vdd N1 A Out BAD IDEA P1 Principles of VLSI Design Basics CMPE 413 6 UMBC U M B C U N IV E R S I...
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This note was uploaded on 08/23/2009 for the course CMSC 711 taught by Professor Chintanpatel during the Fall '04 term at UMBC.

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c1_basics - Principles of VLSI Design Basics CMPE 413 1...

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