chap2_1 - Principles of VLSI Design Details of the MOS...

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Unformatted text preview: Principles of VLSI Design Details of the MOS Transistor CMPE413 1 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 MOS Transistor Definitions n-type MOS: Majority carriers are electrons. p-type MOS: Majority carriers are holes. Positive/negative voltage applied to the gate (with respect to substrate) enhances the number of electrons/holes in the channel and increases con- ductivity between source and drain. V t defines the voltage at which a MOS transistor begins to conduct. For volt- ages less than V t (threshold voltage), the channel is cut off. gate-to-source voltage (V gs ) Drain (I ds ) Current V tn n-channel enhancement MOS-V tp Drain (I ds ) Current p-channel enhancement MOS gate-to-source voltage (V gs ) Assume source-to-drain voltage (V ds ) is fixed Principles of VLSI Design Details of the MOS Transistor CMPE413 2 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 MOS Transistor Definitions In normal operation, a positive voltage applied between source and drain (V ds ). No current flows between source and drain (I ds = 0) with V gs = 0 because of back to back pn junctions. For n-MOS, with V gs > V tn , electric field attracts electrons creating channel. Channel is p-type silicon which is inverted to n-type by the electrons attracted by the electric field. Source Drain Gate V gs V ds Gate Oxide n+ n+ p-substrate n-channel GND Drain Source I ds I ds GND n-MOS transistor Poly Principles of VLSI Design Details of the MOS Transistor CMPE413 3 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 n-MOS Enhancement Transistor Physics Three modes based on the magnitude of V gs : accumulation, depletion and inversion. Source Drain Gate V gs = 0 GND GND Accumulation Mode Poly- + V ds = 0- + n-MOS transistor + + + + + + + + + + + + + + + + + + + + + +------ + + + + + + + + + + + + + + + + + + Principles of VLSI Design Details of the MOS Transistor CMPE413 4 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 n-MOS Enhancement Transistor Physics Source Drain Gate V gs > 0 and V gs <= V t GND GND Depletion Mode Poly- + V ds = 0- + n-MOS transistor depletion region + + + + + + + + + + + + + + + +------ + + + + + + + + + + + + + + + + Source Drain Gate V gs > V t GND GND Inversion Mode Poly- + V ds = 0- + n-MOS transistor depletion region inversion region + + + + + + + +---------------- + + + + + + + + + + + + + + + + Principles of VLSI Design Details of the MOS Transistor CMPE413 5 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 n-MOS Enhancement Transistor With V ds non-zero, the channel becomes smaller closer to the drain. When V ds <= V gs- V t (e.g. V ds = 3V, V gs = 5V and V t = 1V), the channel reaches the drain (since V gd > V t ). This is termed linear , resistive or nonsaturated region. I ds is a function of both V gs and V ds . Source Drain Gate V gs > V t GND GND Inversion Mode...
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chap2_1 - Principles of VLSI Design Details of the MOS...

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