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Unformatted text preview: Principles of VLSI Design Performance Estimation CMPE 413 1 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Introduction Needsimplemodelstoestimatesystemperformanceintermsofsignaldelay and power dissipation. Issues include: Resistance, capacitance and inductance calculations. Delay estimations. Determination of conductor size for power and clock distribution. Power consumption. Charge sharing mechanisms. Design Margining. Reliability. Effects of scaling. Principles of VLSI Design Performance Estimation CMPE 413 2 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Resistance Estimation The resistance of a uniform slab of conducting material may be expressed as For example, in a layout editor, such as magic or virtuoso: R t l w Ohms = where = resistivity t = thickness l/w = length/width Alternatively as R R S l w Ohms = where R S = sheet resistance in ohms/square. is equivalent to 2 8 16 4 Metal1/Metal2 0.07 material /sq Metal 3 Poly Diffusion nwell 0.04 20 25 2K 0.5 to 1.0 processes Typical sheet resistances of contacts => 0.25 to 20 ohms. Irregular shapes require more elaborate calculation  see text for examples. Principles of VLSI Design Performance Estimation CMPE 413 3 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Resistance Estimation Channel resistance can be estimated in the linear region as: A range of 1,000 to 30,000 ohms/square are possible for nchannel and p channel devices. Typicalbetasforidenticallysizeddevices;ndev:~90,pdev:~30microA/V 2 . Temperature changes both mu (mobility) and V t (threshold voltage) and, therefore channel resistance. Channel resistance increases with temperature, approximately +0.25% per degree C above 25 degrees. Metal and poly resistance change about 0.3% and well diffusions about 1% per degree C. R c 1 C ox V gs V t ( 29 L W Ohms 1 V gs V t ( 29 Ohms = = Principles of VLSI Design Performance Estimation CMPE 413 4 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Capacitance Estimation Switching speed of MOS systems strongly dependent: Parasitic capacitances associated with the MOS transistor. Interconnect capacitance of "wires". Resistance of transistors and wires. Total load capacitance on the output of a CMOS gate is sum of: Gate capacitance (of receiver logic gates downstream). Driver diffusion (source/drain) capacitance. Routing ( line ) capacitance of substrate and other wires. Lets consider approximations of each of these capacitances and subsequent approximations of delay based on these expressions. Driver C s and C d Line capacitance Receivers C g Principles of VLSI Design Performance Estimation CMPE 413 5 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T...
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 Fall '04
 ChintanPatel

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