This preview shows pages 1–5. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: Principles of VLSI Design Performance Estimation CMPE 413 1 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Transistor Sizing So far, we have assumed that to get symmetric rise and fall times: Does this rule reduce overall delay ? Therefore, in selfloaded circuits (circuits without significant routing capaci tance and fanouts), equal sized devices can be used to reduce power dissipa tion and area without sacrificing performance (overall delay). W p 2 3 → ( 29 W n × ≈ W p 2 W n = Assume G 1 G 2 3C eq 3C eq W p W n = Assume G 1 G 2 2C eq 2C eq t inv pair – t fall t rise + = 3C eq C eq = C d + C g R 1 2 + ( 29 C eq 2 R 2 1 2 + ( 29 C eq + = = 6 RC eq R 1 1 + ( 29 C eq 2 R 1 1 + ( 29 C eq + = = 6 RC eq Half the resistance since p is twice as wide but twice the resistance per unit area. Principles of VLSI Design Performance Estimation CMPE 413 2 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Stage Ratio How do we drive large load capacitances, e.g. offchip wires via the I/O pads, long buses, etc. ? By using a chain of inverters, where each successive inverter is larger than the previous one. What is the optimal value of a (the stage ratio) that both • Minimizes the delay through the chain. • Minimizes the area and power. The magic number a is e (~2.7)  see analysis in book. The optimal value may vary depending on process parameters. G 1 G 2 1 a G 3 a 2 G 4 a 3 Principles of VLSI Design Performance Estimation CMPE 413 3 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Power Dissipation Two components of power dissipation in CMOS circuits: Static power Dynamic power Static power dissipation: Reversebias leakage current through parasitic diodes formed by source/ drain diffusion and nwell diffusion. Throughcurrent of pseudonMOS devices. Subthreshold conduction (current that flows when V in < V tn ). Becoming more important as power supply is scaled down. Principles of VLSI Design Performance Estimation CMPE 413 4 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Static Dissipation Reversebias leakage current Total Static Power dissipation:...
View
Full
Document
This note was uploaded on 08/23/2009 for the course CMSC 711 taught by Professor Chintanpatel during the Fall '04 term at UMBC.
 Fall '04
 ChintanPatel

Click to edit the document details