chap5_1 - Advanced VLSI Design CMOS Circuit Design CMPE 413...

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Unformatted text preview: Advanced VLSI Design CMOS Circuit Design CMPE 413 1 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Introduction Sofarwehavelookedatfullcomplementarylogicstructuresandtheratioed CMOS inverter. Alternative CMOS logic configurations are also possible when designs are constrained by: High-speed requirements Low-power dissipation Area or density Full-complementary CMOS will always function correctly even in the pres- ence of noise and with low power-supply voltages . "Safeness" of function. In contrast, alternative CMOS logic configurations can produce incorrect functional behavior as a result of: Insufficient power supplies or power supply noise. Noise on gate inputs. Incorrect ratios in ratioed logic. Charge sharing or incorrect clocking in dynamic gates. Advanced VLSI Design CMOS Circuit Design CMPE 413 2 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Temporal Aspects of Design Both functional and temporal (timing) constraints must be met to ensure cor- rect operation of an integrated logic gate. When optimizing for speed, there are many more options from which to choose. Our previous analysis determined that rise/fall time could be approximated by: The number and size of transistors in series (or parallel) in the pull-down or pull-up path affects . C L is affected by the size of the transistors in the gate (self-loading), the rout- ing capacitance and the number and size of the driven transistors. Note this approximation does not consider rise/fall time of the input signal. t f k C L eff V DD------------------------ = eff Advanced VLSI Design CMOS Circuit Design CMPE 413 3 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Temporal Aspects of Design In many designs, many logic paths do not require any special consideration. Critical paths : Paths that require attention to the timing details. Automated design tools such as timing analyzers can automatically identify the slowest paths. Timing analysis can be performed at the: Architecture level. RTL/logic gate level. Circuit level. Layout level. Timing optimization has greatest impact if performed at the architecture level. This requires knowledge of: How many gate delays fit into a clock cycle. How fast addition occurs. How fast memories access. Advanced VLSI Design CMOS Circuit Design CMPE 413 4 UMBC U M B C U N IV E R S I T Y O F M A R Y L A N D B A L T IM ORE COU NTY 1 9 6 6 Temporal Aspects of Design Timing optimization can also be performed at the RTL/logic level where design is focused on: Pipelining. The types of gates (INVERTER, NAND/AND, Complex gates, PLAs, etc.) The fan-in and fan-out of the gates. Circuit level optimization: Sizing transistors. Using alternative forms of CMOS logic. Layout level optimization: Critical paths are routed first to keep their interconnect distance small. Loading capacitance and interconnect resistance considered more exten- sively, e.g., drain merging, choice of routing layer, etc. Advanced VLSI Design...
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chap5_1 - Advanced VLSI Design CMOS Circuit Design CMPE 413...

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