CA-project - Multithreaded Coprocessor Interface for...

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1 Multithreaded Coprocessor Interface for Dual-Core Multimedia SoC Student: Chih-Hung Cho Advisor: Prof. Chih-Wei Liu VLSI Signal Processing Group, DEE, NCTU
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2/27 Outline ± Introduction ± Multithreaded Coprocessor Interface ± Simulation & Implementation Results
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3/27 Introduction ± Dual-core/Multi-core SoC is the possible solution for modern mobile multimedia systems ± Task divergence in most embedded systems drives the heterogeneous computing platform ² Control-oriented task vs. computation-intensive task ² RISC + DSP, “play the right thing in the right place” [1] ² Example: TI OMAP ± RISC: ARM9 ± DSP: TI C’5x TI C'5x DSP ARM926 Shared Memory Controller/DMA 2D Graphics Accelerator Timer, Interrupt Controller, RTC Frame Buffer/Internal SRAM TI OMAP Processor [1]. J. Shandle, “The give and take of DSP processors,” IEEE Signal Processing Mag., vol.17, pp. 43-51, March 2000
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4/27 Low DSP Utilization Problem (1/2) ± Peak vs. delivered performance gap increasing ² Instruction latency & data dependency ² Limits to ILP seem to limit to 3~6-issue for practical options ² DSP utilization is below 50% [2] ± IPC (Inter-Processor Communication) latency ± Memory latency ± Pipeline latency )
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This note was uploaded on 08/23/2009 for the course IEE 5513 taught by Professor Cwliu during the Spring '09 term at National Chiao Tung University.

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CA-project - Multithreaded Coprocessor Interface for...

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