Lecture_03_Pipelining - 5008: Computer Architecture...

Info iconThis preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon
CA Lecture03 - pipelining (cwliu@twins.ee.nctu.edu.tw) 03-1 5008: Computer Architecture 5008: Computer 5008: Computer Architecture Architecture Appendix A Appendix A Pipelining Pipelining
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CA Lecture03 - pipelining (cwliu@twins.ee.nctu.edu.tw) 03-2 Why Pipeline? Because the resources are there! I n s t r. O r d e r Time (clock cycles) Inst 0 Inst 1 Inst 2 Inst 4 Inst 3 ALU Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Single cycle data path
Background image of page 2
CA Lecture03 - pipelining (cwliu@twins.ee.nctu.edu.tw) 03-3 Pipeline Review A pipeline is like an hooked assembly line. Pipelining, in general, is not visible to the programmer (vs ILP) Pipelining doesn t help latency of single task, it helps throughput of entire workload Pipeline rate limited by slowest pipeline stage Multiple tasks operating simultaneously using different resources Potential speedup = Number pipe stages, if perfectly balanced stage. Unbalanced lengths of pipe stages reduces speedup Time to fill pipeline and time to drain it reduces speedup Stall for Dependences
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CA Lecture03 - pipelining (cwliu@twins.ee.nctu.edu.tw) 03-4 Outline MIPS An ISA example for pipelining 5 stage pipelining Structural and Data Hazards Forwarding Branch Schemes Exceptions and Interrupts Conclusion
Background image of page 4
CA Lecture03 - pipelining (cwliu@twins.ee.nctu.edu.tw) 03-5 A "Typical" RISC ISA 32-bit fixed format instruction (3 formats) 32 32-bit GPR (R0 contains zero, DP take pair) 3-address, reg-reg arithmetic instruction Single address mode for load/store: base + displacement no indirection Simple branch conditions Delayed branch see: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM PowerPC, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CA Lecture03 - pipelining (cwliu@twins.ee.nctu.edu.tw) 03-6 Example: MIPS ( - MIPS) Op 31 26 0 15 16 20 21 25 Rs1 Rd immediate Op 31 26 0 25 Op 31 26 0 15 16 20 21 25 Rs1 Rs2 target Rd Opx Register-Register 5 6 10 11 Register-Immediate Op 31 26 0 15 16 20 21 25 Rs1 Rs2/Opx immediate Branch Jump / Call
Background image of page 6
CA Lecture03 - pipelining (cwliu@twins.ee.nctu.edu.tw) 03-7 Datapath vs Control Datapath: Storage, FU, interconnect sufficient to perform the desired functions Inputs are Control Points Outputs are signals Controller: State machine to orchestrate operation on the data path Based on desired function and signals Datapath Controller Control Points signals
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CA Lecture03 - pipelining (cwliu@twins.ee.nctu.edu.tw) 03-8 Approaching an ISA Instruction Set Architecture Defines set of operations, instruction format, hardware supported data types, named storage, addressing modes, sequencing Meaning of each instruction is described by RTL on architected registersand memory Given technology constraints assemble adequate datapath Architected storage mapped to actual storage Function units to do all the required operations Possible additional storage (eg. MAR, MBR, ) Interconnect to move information among regs and FUs Map each instruction to sequence of RTLs
Background image of page 8
Image of page 9
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 08/23/2009 for the course IEE 5513 taught by Professor Cwliu during the Spring '09 term at National Chiao Tung University.

Page1 / 68

Lecture_03_Pipelining - 5008: Computer Architecture...

This preview shows document pages 1 - 9. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online