Lecture_04_Instruction-level Parallelism and its Exploitation_Dynamic

Lecture_04_Instruction-level Parallelism and its Exploitation_Dynamic

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CA Lecture04 - ILP-dynamic (cwliu@twins.ee.nctu.edu.tw) 04-1 5008: Computer Architecture 5008: Computer 5008: Computer Architecture Architecture Chapter 2 Chapter 2 Instruction Instruction - - Level Level Parallelism and Its Exploitation Parallelism and Its Exploitation
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CA Lecture04 - ILP-dynamic (cwliu@twins.ee.nctu.edu.tw) 04-2 Outline ILP Compiler techniques to increase ILP Loop Unrolling Static Branch Prediction Dynamic Branch Prediction Overcoming Data Hazards with Dynamic Scheduling (Start) Tomasulo Algorithm Conclusion
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CA Lecture04 - ILP-dynamic (cwliu@twins.ee.nctu.edu.tw) 04-3 Recall from Pipelining Review • Pipeline CPI = Ideal pipeline CPI + Structural Stalls + Data Hazard Stalls + Control Stalls – Ideal pipeline CPI : measure of the maximum performance attainable by the implementation – Structural hazards : HW cannot support this combination of instructions – Data hazards : Instruction depends on result of prior instruction still in the pipeline – Control hazards : Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps)
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CA Lecture04 - ILP-dynamic (cwliu@twins.ee.nctu.edu.tw) 04-4 Instruction-Level Parallelism • The technique of increasing the ability of the processor to exploit parallelism among instructions. To overlap the execution of instructions to improve performance – To reduce the impact of data and control hazards 2 approaches to exploit ILP Rely on hardware to help discover and exploit the parallelism dynamically : • depend on the hardware to locate the parallelism e.g., Pentium 4, AMD Opteron, IBM Power Rely on software technology to find parallelism, statically at compile-time : • determine the parallelism at compiler time e.g., Itanium 2
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CA Lecture04 - ILP-dynamic (cwliu@twins.ee.nctu.edu.tw) 04-5 Instruction-Level Parallelism (ILP) • Basic Block (BB) ILP is quite small : – BB: a straight-line code sequence with no branches in except to the entry and no branches out except at the exit – average dynamic branch frequency 15% to 25% => 4 to 7 instructions execute between a pair of branches – Plus instructions in BB likely to depend on each other We must exploit ILP across multiple basic blocks – Loop unrolling to exploit loop-level parallelism • By compiler, statistically • By hardware, dynamically – Vector instructions • The long latency of each vector instruction can be pipelined and operated in parallel for (i=1; i<=1000, i=i+1) x[i] = x[i] + y[i] x[1] = x[1] + y[1] x[2] = x[2] + y[2] x[1000]=x[1000]+y[1000] Loop-level parallelism
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CA Lecture04 - ILP-dynamic (cwliu@twins.ee.nctu.edu.tw) 04-6 Data Dependences and Parallelisms • If 2 instructions are parallel – they can execute simultaneously in a pipeline without causing any stalls (except the structural hazards) – their execution order can be swapped • If 2 instructions are dependent –they must execute in order or partially overlapped.
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This note was uploaded on 08/23/2009 for the course IEE 5513 taught by Professor Cwliu during the Spring '09 term at National Chiao Tung University.

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Lecture_04_Instruction-level Parallelism and its Exploitation_Dynamic

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