Lecture_05_Instruction-level Parallelism and its Exploitation_cont

Lecture_05_Instruction-level Parallelism and its Exploitation_cont

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CA Lecture05 - ILP ([email protected]) 05-1 5008: Computer Architecture 5008: Computer 5008: Computer Architecture Architecture Chapter 2 Chapter 2 Instruction Instruction - - Level Level Parallelism and Its Exploitation Parallelism and Its Exploitation
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CA Lecture05 - ILP ([email protected]) 05-2 Review from Last Lecture Instruction Level Parallelism Leverage implicit parallelism for performance: Loop unrolling by compiler to increase ILP Branch prediction to increase ILP Dynamic HW exploiting ILP Works when can t know dependence at compile time Can hide L1 cache misses Code for one machine runs well on another
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CA Lecture05 - ILP ([email protected]) 05-3 Review from Last Lecture Reservations stations: renaming to larger set of registers + buffering source operands Prevents registers as bottleneck Avoids WAR, WAW hazards Allows loop unrolling in HW Not limited to basic blocks Helps cache misses as well Lasting Contributions Dynamic scheduling Register renaming Load/store disambiguation
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CA Lecture05 - ILP ([email protected]) 05-4 Outline Review Speculation Speculative Tomasulo Example Memory Aliases Exceptions VLIW Advanced Techniques for Instruction Delivery and Speculation Summary
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CA Lecture05 - ILP ([email protected]) 05-5 Greater ILP ? Essentially a data flow execution model : Operations execute as soon as their operands are available Greater ILP: Overcome control dependence by hardware speculating on outcome of branches and executing program as if guesses were correct Speculation fetch, issue, and execute instructions as if branch predictions were always correct Dynamic scheduling only fetches and issues instructions
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CA Lecture05 - ILP ([email protected]) 05-6 Speculation to greater ILP 3 components of HW-based speculation: 1. Dynamic branch prediction to choose which instructions to execute 2. Speculation to allow execution of instructions before control dependences are resolved + ability to undo effects of incorrectly speculated sequence 3. Dynamic scheduling to deal with scheduling of different combinations of basic blocks
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CA Lecture05 - ILP ([email protected]) 05-7 Adding Speculation to Tomasulo Must separate execution from allowing instruction to finish or commit This additional step called instruction commit When an instruction is no longer speculative, allow it to update the register file or memory Requires additional set of buffers to hold results of instructions that have finished execution but have not committed This reorder buffer ( ROB ) is also used to pass results among instructions that may be speculated
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CA Lecture05 - ILP ([email protected]) 05-8 The Speculative MIPS Replace store buffer
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CA Lecture05 - ILP ([email protected]) 05-9 Observations • For an execution result, separate – data forwarding (thru RS) path – write-back (thru ROB) path • Data forwarding path
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Lecture_05_Instruction-level Parallelism and its Exploitation_cont

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