Lecture_09_Multiprocessors and Task-level parallelism_II

Lecture_09_Multiprocessors and Task-level parallelism_II -...

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CA Lecture08 - multiprocessors and TLP (cwliu@twins.ee.nctu.edu.tw) 09-1 5008: Computer Architecture 5008: Computer 5008: Computer Architecture Architecture Chapter 4 Chapter 4 Multiprocessors and Multiprocessors and Thread Thread - - Level Parallelism Level Parallelism -- -- II II
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CA Lecture08 - multiprocessors and TLP (cwliu@twins.ee.nctu.edu.tw) 09-2 Review Caches contain all information on state of cached memory blocks Snooping cache over shared medium for smaller MP by invalidating other cached copies on write Sharing cached data Coherence (values returned by a read), Consistency (when a written value will be returned by a read)
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CA Lecture08 - multiprocessors and TLP (cwliu@twins.ee.nctu.edu.tw) 09-3 Coherency Misses 1. True sharing misses arise from the communication of data through the cache coherence mechanism Invalidates due to 1 st write to shared block Reads by another CPU of modified block in different cache Miss would still occur if block size were 1 word 2. False sharing misses when a block is invalidated because some word in the block, other than the one being read, is written into Invalidation does not cause a new value to be communicated, but only causes an extra cache miss Block is shared, but no word in block is actually shared miss would not occur if block size were 1 word
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CA Lecture08 - multiprocessors and TLP (cwliu@twins.ee.nctu.edu.tw) 09-4 Example: True vs. False Sharing vs. Hit? Read x2 5 Write x2 4 Write x1 3 Read x2 2 Write x1 1 True, False, Hit? Why? P2 P1 Time Assume x1 and x2 in same cache block. P1 and P2 both read x1 and x2 before. True miss; invalidate x1 in P2 False miss; x1 irrelevant to P2 False miss; x1 irrelevant to P2 False miss; x1 irrelevant to P2 True miss; invalidate x2 in P1
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CA Lecture08 - multiprocessors and TLP (cwliu@twins.ee.nctu.edu.tw) 09-5 Outline Review Directory-based protocols and examples Synchronization Relaxed Consistency Models Conclusion
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CA Lecture08 - multiprocessors and TLP (cwliu@twins.ee.nctu.edu.tw) 09-6 A Cache Coherent System Must: Provide set of states, state transition diagram, and actions Manage coherence protocol (0) Determine when to invoke coherence protocol (a) Find info about state of block in other caches to determine action whether need to communicate with other cached copies (b) Locate the other copies (c) Communicate with those copies (invalidate/update) (0) is done the same way on all systems state of the line is maintained in the cache protocol is invoked if an access fault occurs on the line Different approaches distinguished by (a) to (c)
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CA Lecture08 - multiprocessors and TLP (cwliu@twins.ee.nctu.edu.tw) 09-7 Bus-based Coherence All of (a), (b), (c) done through broadcast on bus faulting processor sends out a search others respond to the search probe and take necessary action Could do it in scalable network too
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Lecture_09_Multiprocessors and Task-level parallelism_II -...

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