Lecture_10_Memory Hierarchy Design

Lecture_10_Memory Hierarchy Design - 5008: Computer...

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CA Lecture10 - memory hierarchy design (cwliu@twins.ee.nctu.edu.tw) 10-1 5008: Computer Architecture 5008: Computer 5008: Computer Architecture Architecture Chapter 5 Chapter 5 Memory Hierarchy Memory Hierarchy Design Design
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CA Lecture10 - memory hierarchy design (cwliu@twins.ee.nctu.edu.tw) 10-2 Outline 11 Advanced Cache Optimizations Memory Technology and DRAM Optimizations Virtual Machines Conclusion
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CA Lecture10 - memory hierarchy design (cwliu@twins.ee.nctu.edu.tw) 10-3 Why More on Memory Hierarchy? 1 10 100 1,000 10,000 100,000 1980 1985 1990 1995 2000 2005 2010 Year Performance Mem ory Processor Processor-Memory Performance Gap Growing
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CA Lecture10 - memory hierarchy design (cwliu@twins.ee.nctu.edu.tw) 10-4 Review: 6 Basic Cache Optimizations Reducing hit time 1. Giving Reads Priority over Writes E.g., Read complete before earlier writes in write buffer 2. Avoiding Address Translation during Cache Indexing Reducing Miss Penalty 3. Multilevel Caches Reducing Miss Rate 4. Larger Block size (Compulsory misses) 5. Larger Cache size (Capacity misses) 6. Higher Associativity (Conflict misses)
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CA Lecture10 - memory hierarchy design (cwliu@twins.ee.nctu.edu.tw) 10-5 11 Advanced Cache Optimizations Reducing hit time 1. Small and simple caches 2. Way prediction 3. Trace caches Increasing cache bandwidth 4. Pipelined caches 5. Multibanked caches 6. Nonblocking caches Reducing Miss Penalty 7. Critical word first 8. Merging write buffers Reducing Miss Rate 9. Compiler optimizations Reducing miss penalty or miss rate via parallelism 10.Hardware prefetching 11.Compiler prefetching
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10-6 1. Fast Hit times via Small and Simple Caches Index tag memory and then compare takes time Small cache can help hit time since smaller memory takes less time to index E.g., L1 caches same size for 3 generations of AMD microprocessors: K6, Athlon, and Opteron Also L2 cache small enough to fit on chip with the processor avoids time penalty of going off chip Simple direct mapping Can overlap tag check with data transmission since no choice Access time estimate for 90 nm using CACTI model 4.0 Median ratios of access time relative to the direct-mapped caches are 1.32, 1.39, and 1.43 for 2-way, 4-way, and 8-way caches - 0.50 1.00 1.50 2.00 2.50 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB 1 MB Cache size Access time (ns) 1-way 2-way 4-way 8-way
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CA Lecture10 - memory hierarchy design (cwliu@twins.ee.nctu.edu.tw) 10-7 2. Fast Hit times via Way Prediction How to combine fast hit time of Direct Mapped and have the lower conflict misses of 2-way SA cache? Way prediction : keep extra bits in cache to predict the way, or block within the set, of next cache access. Multiplexor is set early to select desired block, only 1 tag comparison performed that clock cycle in parallel with reading the cache data Miss 1 st check other blocks for matches in next clock cycle Accuracy 85% Drawback: CPU pipeline is hard if hit takes 1 or 2 cycles Used for instruction caches vs. data caches Hit Time Way-Miss Hit Time Miss Penalty
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CA Lecture10 - memory hierarchy design (cwliu@twins.ee.nctu.edu.tw)
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This note was uploaded on 08/23/2009 for the course IEE 5513 taught by Professor Cwliu during the Spring '09 term at National Chiao Tung University.

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Lecture_10_Memory Hierarchy Design - 5008: Computer...

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