Lecture 05A- simple implementation

Lecture 05A- simple implementation - 1048: Computer...

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Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw) 5A-1 1048: Computer Organization 1048: Computer 1048: Computer Organization Organization Lecture 5 Lecture 5 Datapath Datapath and and Control Control
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Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw) 5A-2 Introduction • In this lecture, we will try to implement simplified MIPS which contain – Memory reference instructions: lw, sw – Control flow instructions: beg, j – Arithmetic-logical instructions: add, sub, and, or, slt •D e s i g n p r i n c i p l e s – Make the common case fast – Simplicity favors regularity • Two types of circuits/function units – Combinational: elements that operate on data values – Sequential: elements that contain state
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Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw) 5A-3 Outline • Part A: Designing a Single-Cycle Processor • Part B: Designing a Multicycle Processor
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Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw) 5A-4 Part A Outline • Designing a processor • Building the datapath • A single-cycle implementation • Control for the single-cycle CPU – Control of CPU operations – ALU controller – Main controller
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Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw) 5A-5 How to Design a Processor? 1. Analyze instruction set (datapath requirements) – The meaning of each instruction is given by the register transfers – Datapath must include storage element – Datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points effecting register transfer 5. Assemble the control logic
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5A-6 • All MIPS instructions are 32 bits long with 3 formats: –R - t y p e : –I - t y p e : –J - t y p e : • The different fields are: – op: operation of the instruction – rs, rt, rd: source and destination register – shamt: shift amount – funct: selects variant of the “op” field – address / immediate – target address: target address of jump op target address 0 26 31 6 bits 26 bits op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits Step 1: Analyze Instruction Set
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Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw) 5A-7 op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits op address 0 16 21 26 31 6 bits 26 bits Our Example: A MIPS Subset •R - T y p e : add rd, rs, rt sub rd, rs, rt and rd, rs, rt or rd, rs, rt slt rd, rs, rt Load/Store: lw rt,rs,imm16 sw rt,rs,imm16 •I m m o p e r a n d : addi rt,rs,imm16 •B r a n c h : beq rs,rt,imm16 •J u m p : j target
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Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw) 5A-8 Logical Register Transfers MEM[ PC ] = op | rs | rt | rd | shamt | funct or = op | rs | rt | Imm16 or = op | Imm26 (added at the end) Inst Register transfers ADD R[rd] <- R[rs] + R[rt]; PC <- PC + 4 SUB
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This note was uploaded on 08/23/2009 for the course DEE 4641 taught by Professor Cwliu during the Fall '08 term at National Chiao Tung University.

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Lecture 05A- simple implementation - 1048: Computer...

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