Lecture 05B- multicycle implementation

Lecture 05B- multicycle implementation - 1048: Computer...

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Lecture05B - multicycle implementation (cwliu@twins.ee.nctu.edu.tw) 5B-1 1048: Computer Organization 1048: Computer 1048: Computer Organization Organization Lecture 5 Lecture 5 Datapath Datapath and and Control Control
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Lecture05B - multicycle implementation (cwliu@twins.ee.nctu.edu.tw) 5B-2 Recap: A Single-Cycle Processor CPI=1 PC Instruction memory Read address Instruction 16 32 Add ALU result M u x Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Shift left 2 4 M u x ALU operation 3 RegWrite MemRead MemWrite PCSrc ALUSrc MemtoReg ALU result Zero ALU Data memory Address Write data Read data M u x Sign extend Add 4
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Lecture05B - multicycle implementation (cwliu@twins.ee.nctu.edu.tw) 5B-3 •L o n g c y c l e t i m e • All instructions take same time as the slowest path • Real memory is not so ideal – cannot always get job done in one (short) cycle • An FU can only be used once => higher cost PC Inst Memory mux ALU Data Mem mux PC Reg File Inst Memory mux ALU mux PC Inst Memory mux ALU Data Mem PC Inst Memory cmp mux Reg File Reg File Reg File Arithmetic & Logical Load Store Branch Critical Path setup setup What’s Wrong with Single-cycle?
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Lecture05B - multicycle implementation (cwliu@twins.ee.nctu.edu.tw) 5B-4 Multicycle Approach • Break up the instructions into steps, each step takes a cycle – balance the amount of work to be done – restrict each cycle to use only one major functional unit – share function units within the execution of a single instructions • Add multiplexor for sharing datapath • At the end of a cycle – store values for use in later cycles (easiest thing to do) – introduce additional internal registers
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Lecture05B - multicycle implementation (cwliu@twins.ee.nctu.edu.tw) 5B-5 Outline • Part A: Designing a Single-Cycle Processor • Part B: Designing a Multicycle Processor
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Lecture05B - multicycle implementation (cwliu@twins.ee.nctu.edu.tw) 5B-6 Part B Outline • A multicycle implementation – Multicycle datapath – Multicycle execution steps – Multicycle control (Appendix C.3) • Microprogramming: simplifying control (Appendix C.4) • Exceptions
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5B-7 • Reduce cycle time • Diff. Inst. take diff. cycles •S h a r e f u n c t i o n a l u n i t s Multicycle Implementation storage element Acyclic Combinational Logic storage element storage element Acyclic Combinational Logic (A) storage element storage element Acyclic Combinational Logic (B) =>
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Partition Single-Cycle Datapath PC Instruction memory Read address Instruction 16 32 Add ALU result M u x Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Shift left 2 4 M u x ALU operation 3 RegWrite MemRead MemWrite PCSrc ALUSrc MemtoReg ALU result Zero ALU Data memory Address Write data Read data M u x Sign extend Add Ins. fetch RF access ALU operation memory access • Add registers between smallest steps 4
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Lecture05B - multicycle implementation (cwliu@twins.ee.nctu.edu.tw) 5B-9 Multicycle Datapath • 1 memory (instr. & data), 1 ALU (addr, PC+4, add,…),
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Lecture 05B- multicycle implementation - 1048: Computer...

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