Lecture 06-pipelining - 1048: Computer Organization Lecture...

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Lecture06 - pipelining (cwliu@twins.ee.nctu.edu.tw) 6-1 1048: Computer Organization 1048: Computer 1048: Computer Organization Organization Lecture 6 Lecture 6 Pipelining Pipelining
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Lecture06 - pipelining (cwliu@twins.ee.nctu.edu.tw) 6-2 Outline An overview of pipelining An overview of pipelining • A pipelined datapath • Pipelined control • Data hazards and forwarding • Data hazards and stalls • Branch hazards • Exceptions • Superscalar and dynamic pipelining
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• Laundry example: Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Dryer takes 40 minutes “Folder” takes 20 minutes A B C D Pipelining Is Natural!
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• Sequential laundry takes 6 hours for 4 loads • If they learned pipelining, how long would it take? A B C D 30 40 20 30 40 20 30 40 20 30 40 20 6 PM 78 9 10 11 Midnight T a s k O r d e r Time Sequential Laundry
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• Pipelined laundry takes 3.5 hours for 4 loads A B C D 6 PM 78 9 10 11 Midnight T a s k O r d e r Time 30 40 40 40 40 20 Pipelined Laundry: Start ASAP
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Pipelining Lessons •Doesn ’t he lp latency of single task, but throughput of entire • Pipeline rate limited by slowest stage •Mu lt ip le tasks working at same time using different resources • Potential speedup = Number pipe stages • Unbalanced stage length; time to fill & drain the pipeline reduce speedup • Stall for dependences A B C D 6 PM 78 9 T a s k O r d e r Time 30 40 40 40 40 20
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Single-, Multi-Cycle, vs. Pipeline Clk Cycle 1 Multiple Cycle Implementation: Ifetch Reg Exec Mem Wr Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Load Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem Load Store Pipeline Implementation: Ifetch Reg Exec Mem Wr Store Clk Single Cycle Implementation: Load Store Waste Ifetch R-type Ifetch Reg Exec Mem Wr R-type Cycle 1 Cycle 2
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Lecture06 - pipelining (cwliu@twins.ee.nctu.edu.tw) 6-8 Pipelining MIPS Execution Instruction fetch Reg ALU Data access 8 ns Instruction fetch access Instruction fetch Time lw $1, 100($0) lw $2, 200($0) lw $3, 300($0) 2 4 6 8 10 12 14 16 18 2 4 6 8 14 ... Program execution order (in instructions) Instruction fetch ALU access Time 2 ns Instruction fetch ALU access 2 ns Instruction fetch ALU 2 ns 2 ns 2 ns 2 ns 2 ns (in instructions) Fig. 6.3
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I n s t r. O r d e r Time (clock cycles) Inst 0 Inst 1 Inst 2 Inst 4 Inst 3 ALU Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Why Pipeline? Single- cycle Datapath Because the Resources Are There!
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Lecture06 - pipelining (cwliu@twins.ee.nctu.edu.tw) 6-10 Outline • An overview of pipelining A pipelined A pipelined datapath datapath • Pipelined control • Data hazards and forwarding • Data hazards and stalls • Branch hazards • Exceptions • Superscalar and dynamic pipelining
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Lecture06 - pipelining (cwliu@twins.ee.nctu.edu.tw) 6-11 Designing a Pipelined Processor • Examine the datapath and control diagram – Starting with single- or multi-cycle datapath?
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Lecture 06-pipelining - 1048: Computer Organization Lecture...

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