EE6325fall06 - EE 6325 VLSI Design Prof. Carl Sechen Rm....

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EE 6325 VLSI Design Prof. Carl Sechen Rm. 4.902 972-835-1611 carl.sechen@utdallas.edu Office Hours: TuTh 6-7p and by appointment Textbook (not required): Digital Integrated Circuits by J. Rabaey, A. Chandrakasan and B. Nikolic, 2 nd Edition, 2003, Pearson Education (Prentice Hall) Student Learning Objectives: Students will learn to: Analyze MOS device properties and their effects on digital circuit design Analyze the effects of device sizing and parasitics on speed, power and area Analyze the static CMOS inverter Design and layout static CMOS gates Design and layout a complete library of standard cells Apply the method of logical effort to size transistors for circuit perform- ance Design latches and flip-flops Analyze basic clocking and timing issues Analyze other CMOS logic techniques, including dynamic logic Design adders, multipliers, and other arithmetic blocks Design static random access memories (SRAMs) Apply industry-standard VLSI design and analysis tools Design and implement a small standard cell digital IC Lecture Topics (corresponding textbook readings): 1. Review of MOS device operation (3.2.1-4 and 3.3.1-3) 2. CMOS inverter (5.1 through 5.5) 3. Static CMOS gates (6.1 and 6.2.1) 4. Layout of static CMOS gates (pp. 319 – 324) 5. Design of flip-flops (7.1 and 7.2) 6. Other CMOS logic techniques, such as dynamic logic (6.2.2-3 and 6.3) 7. Adders, multipliers, and other arithmetic blocks (11.1 – 11. 4) 8. SRAM design (12.1 – 12. 3) Grading: Exams 55% (three midterms and a one-hour final exam; the weight of the
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final equals the weight of each of the three midterms) o First midterm: Sep. 12 o Second midterm: Oct. 10 o Third midterm: Nov. 9 o Reading for 1 st exam: pp. 4-18, 36-50, 179-228 Projects 45% Projects (due dates): 1. Verilog (or VHDL) design: Aug. 31 2. Inverter design and layout: Sep. 19 3. Synthesizable Verilog (or VHDL) design: Sep. 28 4. Flip-flop design and layout: Oct. 19 5. Cell library design and layout: Nov. 2 6. Final layout (placement and routing) of your design: Nov. 21 Lab for project work: Room 4.308 Teaching Assistant: Jung Kim (room 3.102 or 3.104) The University of Texas System and The University of Texas at Dallas have rules and regulations for the orderly and efficient conduct of their business. It is the responsibility of each student and each stu- dent organization to be knowledgeable about the rules and regulations which govern student conduct and activities. General information on student conduct and discipline is contained in the UTD publica- tion, A to Z Guide , which is provided to all registered students each academic year. The University of Texas at Dallas administers student discipline within the procedures of recognized
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This note was uploaded on 08/23/2009 for the course EE 6235 taught by Professor Carlsechen during the Fall '06 term at University of Texas at Dallas, Richardson.

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EE6325fall06 - EE 6325 VLSI Design Prof. Carl Sechen Rm....

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